FPGA decoupling capacitors - top or bottom?

[aiju]

Having a small-ish BGA FPGA (e.g. XC7A35T) on a 4-layer board is a bit of a recurring theme with my designs and I've been wondering how much it actually matters whether you have decoupling caps on the bottom of the PCB. There is a lot of qualitative statements on this topic but I haven't seen much good quantitative data. Using the formula from [1] I calculated about 2nH extra inductance from placing the caps on the bottom, which seems large enough to matter (parameters: plane spacing 1.2 mm, via hole diameter 0.25 mm, 10 mm distance).

I was wondering whether someone here has done something resembling a controlled experiment and has some data to share.

Some things that I think complicate the picture:
1. tight power/ground plane coupling drastically slashes that 2nH figure (it's proportional to plane spacing) and so the people with fancy pants 20 layer boards have different concerns
2. above around 100 MHz PCB-level decoupling quickly becomes hopeless anyway.
3. some FPGAs have on-chip decoupling.

[1] http://www.sigcon.com/Pubs/edn/ParasiticInductance.htm

[nctnico]

The answer is: it depends. In my designs I have very large copper planes to power things like memory, SoCs and FPGAs to avoid needing capacitors on the bottom side. The capacitors (various values to smear ESR) on the top have 2 vias to the power planes each and are also connected together with copper pours on the top layer. Ofcourse this comes at the expense of board space.

[BrianHG]

If you use small SMD caps which can fit between the vias, like 0402 or 0201, for maximum number of caps minimal noise for each power pin pair and my personal preference, right beneath the BGA.

[Someone]

The trace inductance trying to connect between capacitors around the edge of a BGA and the power pins buried in the middle make capacitors inside the BGA footprint almost essential. Power density demands on these parts aren't as bad as desktop CPUs but they're not far behind.

[ransonjd]

Rick Hartley has some pretty good presentations on this, with decent data and convenient rules of thumb. He makes a living by teaching this stuff, so I can't really share them.

A summary rule of thumb is this (ignoring a lot of convoluting factors): If your planes are more than 10mils apart, the interplane capacitance isn't effective in decoupling, so keep your capacitors as close as possible to the supply pins with the least inductive return path possible. With your planes at 1.2mm apart, this is probably on the opposite side of the board underneath a BGA. If your planes are less than 10 mils apart, make sure your capacitors are within the radius defined by the speed of signal propagation (based on the PCB's dielectric constant), and the fastest rise time of your part. The board capacitance is supplying all of the energy during the edge, and you want your capacitors to start replenishing that energy by the time the edge finishes.

Is there any reason you're not putting your power and return on opposite sides of a prepreg, rather than across the core? It sounds like you're working with a 1.2mm core, so with a standard 1.6mm board, your outer layer pairs are close enough to give effective board capacitance.

[ahbushnell]

If you use small SMD caps which can fit between the vias, like 0402 or 0201, for maximum number of caps minimal noise for each power pin pair and my personal preference, right beneath the BGA.

I agree.  I put them on the back with BGA's.

[aiju]

Is there any reason you're not putting your power and return on opposite sides of a prepreg, rather than across the core? It sounds like you're working with a 1.2mm core, so with a standard 1.6mm board, your outer layer pairs are close enough to give effective board capacitance.

With a signal-prepreg-signal-core-ground-prepreg-power stackup I'd have more coupling between signals and greater trace inductance (especially for signals on the top layer).
I'm not sure that's much better...

[ransonjd]

These are the type of stackup I would consider. I haven't taken a look at the pinout for your part, and I don't know if you're using via-in-pad or HDI, all of which affect feasibility.

Ground
Signal / Power Pours
Signal / Power Pours
Ground

Signal/Power Pours
Ground
Ground
Signal/Power Pours

[aiju]

All my designs so far have used signal - ground - power - signal. Though I guess I've also used signal layers for extra power pours when there's space. I don't really like the thought of losing access to signals for debugging and the occasional bodge.
I can see the benefit of two ground planes but it seems hard to route all the power rails to the FPGA this way -- I can barely manage the way I do it.
You lose the top layer to mostly pads and vias, then all the signal routing happens on the bottom layer and if my prayers are answered the power pins line up so that I can squeeze in the three or four voltages that I need on the power plane without too many dodgy tricks.

I guess if you have via-in-pad or other deep pocket features then you can do it by squeezing signals between the pads.