FPGA development board with ft2232h that can do synchronous fifo

[asgard20032]

I am searching for a development board that has a ft2232h with the channel A routed correctly to do synchronous fifo. Most of the board I saw only allow async fifo because they didn't expose all the required pin... Some may say why not just buy a breakout board with a ft2232h... well, at maximum speed with some long wire, it won't be good for signal integrity... except if someone can tell me the opposite.

Also, got the problem that most module out there surely use counterfeit chip, and with the ftdi brick... don't want to swim in muddy water.

I want to toy a little bit by pushing my fpga at max speed and doing streaming between computer and the fpga.

[xaxaxa]

If you go the custom fpga board route, I'd strongly recommend using a usb phy instead like the usb3343; wiring it to the fpga is very simple (see pic) and using the usb-serial core here: http://jorisvr.nl/article/usb-serial you can get about 30MB/s transfer. I can provide example vhdl that hooks up the core with a ulpi-utmi adapter and gives you a fifo interface.

Since ftdigate I've always avoided ftdi chips (do NOT want to support that kind of corporation), and there are always alternatives which are usually cheaper.

[AndyC_772]

Interesting, I might just have to give that a go. Thanks.

[electro-logic]

Hello, at 60 mhz signal integrity is not impossible, you can start from here http://electro-logic.blogspot.it/2014/02/fpga-comunicazione-ad-alta-velocita_16.html to see a similar example

[asmi]

Or just go "all in" and use FT601 to get 320+ MBytes/s. FTDI sells breakout boards with FMC/HSMC connectors that are compatible with most Antel/Xilinx boards.

[SiliconWizard]

I did this a while ago for prototyping needs with a Mimas FPGA board (from Numato, based on Spartan 6) and an FT232H (single channel) breakout board, plugged onto one of the MIMAS connectors with an intermediate small piece of prototyping PCB. The connections were done manually and were kept at around 20 or 25 mm length max including the connectors. It worked without any issue at the synchronous clock frequency which is 60 MHz.

Signal-wise, if you keep your connections short, you shouldn't have much problem at 60 MHz.

Aside from purely hardware considerations, one thing to keep in mind on the FPGA side is that since the FTDI chip provides the clock in synchronous mode, either you use this same clock throughout your HDL design and that's simple enough, or you have another (or several other) clock(s) not synchronous to the FTDI clock, in which case you have to add synchronization means between the different clock domains. Failing to do so properly will make your design fail and additionally will give you bad headaches.

[laugensalm]

I've run into this issue as well a while back, if I recall correctly, the synchronous FIFO would only work on channel A, so if you're for some reason bound to using JTAG via Port A as well: no such fun.
Also, you might consider the isochronous option (which you can't do with the FT2232), if you have large amounts of data to stream which you can't buffer (like video), that's were the Cypress FX3 (or legacy FX2) are/were popular, but they again require careful programming. Thus, not exactly plug&play, but there are many reference projects to steal from.

[accelc2018]

That is correct. Synchronous FIFO is avaialble only on Channel A and can hit 35 - 40MBytes per second in practical situations. Channel B can do only asynchronous FIFO which is limited to ~5 - 6 MBytes bandwidth.

[mmaroti]

I am planning to use a Lattice FPGA and an FT2232H for SDR and need to have simultaneous 16 mbyte/s TX and 16 mbyte/s RX stream with no samples dropped. Is it possible to use the FT2232H chip with synchronous FIFO on channel A while use channel B for FPGA programming?

I know that with synchronous FIFO you cannot use channel B at all at the same time. Also, according to the datasheet you need to program the external EEPROM to enable asynchronous FIFO and then switch to synchronous FIFO within software. However on page 25 of the datasheet this is written: "Note that Asynchronous FIFO mode must be selected on both channels before selecting the Synchronous FIFO mode in software." This means, that both channels ha to be configured to synchronous FIFO within the EEPROM so channel B cannot be used for FPGA programming. Has anyone experience with this?

[mikeselectricstuff]

Not checked the pin connections but this may be worth a look
http://uk.farnell.com/ftdi/morph-ic-ii/module-development-fpga/dp/1846827