Keeping CE\ low while accessing multiple addresses is fairly common.
Most devices toggle RD\ (OE\) each cycle, but some of them do not, especially when doing burst reads:
Yes. But you are talking high-speed synchronous RAMs here.
This is about old-fashioned parallel asynchronuos SRAMs.
Back in the day, I built a device from a kit which allowed the range of colours displayed by a BBC Micro to be expanded.
The 'beeb' had a digital TTL video output, ie. one bit each for red, green and blue, giving a palette of 8 colours.
To allow different colours to be shown on a compatible monitor, the device used the digital RGB signal to drive the address bits of a small capacity SRAM chip. The data outputs from the SRAM fed DACs for each channel, giving an analogue RGB signal that could show a much wider range of colours.
I no longer have a schematic, but I can easily imagine that the SRAM's CE was permanently enabled, and the data outputs simply changed in time with the video signal.
That's exactly what I meant when I referred to a "PROM-lookup type of circuit". And in your "beeb" extension it was probably a PROM, not an SRAM.
All that aside, the normal application for an asynchronous-interface parallel FRAM would not differ from an SRAM. That was my point.
Cheers.