FPGA pmod DAC

[Bogdan]

Hello everyone,

So here is my problem..
I made this VGA interface from my FPGA to my monitor .It worked great, but i was not quite satisfied with the 8-bit color (256 colors) i was limited to.
So a wild idea came to my mind, why don't i use the pmod (i/o general purpose pins) on my Digilent Nexys 3 FPGA as output pins, and make a little DAC on a breadboard an have like 12-bit colors or more.
I must admit i'm no expert in electronics(this is my first circuit actually), but this idea got me excited and i bought a multimeter, a lot of resistors, wires and a breadboard to make a resistor ladder to divide my voltage.
Everything was fine until i realised that the IO pins(which i can set to '0' or '1' 0v or 3.3v) have a dark secret .An IO pin set to '1' is not the same as the VCC pin (see image bellow).They both should be 3.3v and they are if i measure them separetly with my multimeter, but when in the ladder the VCC pins work great, while the IO pins set to logic '1' (3.3v) go down to 2.9, 3.1 or other values.
I suspect that they somewhat interract with eachother and the ladder makes them go that way...

But i'm kind of lost and i really need your help !
I will attach a picture of the ladder schematic bellow.
Thank you !

[ale500]

The amplitude on the Analog R, G & B pins should swing between 0 and ~750 mV per the spec, ~3 V is way out of spec. On the monitor side the signals have a 75 ohm resistor to ground...

[Bogdan]

thats a valid point, but is not quite the answer to my question
why are my IO pins not fixed to 3.3 volts ? and go down to 2.9, 3.1 where they are connected to the ladder ?

[lincoln]

well the nexus 2 has 75 ohm series resistor as well as the series resistant of the out put driver. The FPGA can also be configure as to how hard to drive the signals. If you are connecting to an R2R ladder with out a buffer you will never see a solid 3.3v at the output because the series Rs and the load Rs are forming a voltage divider.

To solve this you can use a CMOS buffer/invert er to buffer the IO pin form the load. something like 74ahc04.

[ale500]

There are curves showing how the VOH drops with the sinked current, look for instance here:

https://www.fairchildsemi.com/application-notes/AN/AN-77.pdf

Page 2, Figure 2.

That may answer the why .