FPGAs and FIR filters

[Boscoe]

I wrote some code for a 24bit wide FIR filter with 1024 taps for audio. Thing is, one filter is 20 times larger than a 22k LE Altera FPGA. Just as a bit of a sanity check does this sound right or must something be wrong for this to happen?

[suicidaleggroll]

1024 taps is a -LOT-...are you sure you need that many?  Does the Altera have built-in IP for FIRs?  I know Xilinx does, and you can trade off area for speed by feeding it a clock that's faster than the input data rate.  A couple of months ago I used it to implement a 144 tap LPF on an Artix-7.  625 kHz sample rate, 32-bit, dual channel, 40 MHz clock, and it takes up 14 of the 120 DSP slices on a 50k LE Artix-7 (negligible amount of other resources).

[Boscoe]

1024 taps is a -LOT-...are you sure you need that many?  Does the Altera have built-in IP for FIRs?  I know Xilinx does, and you can trade off area for speed by feeding it a clock that's faster than the input data rate.  A couple of months ago I used it to implement a 144 tap LPF on an Artix-7.  625 kHz sample rate, 32-bit, dual channel, 40 MHz clock, and it takes up 14 of the 120 DSP slices on a 50k LE Artix-7 (negligible amount of other resources).

Thanks! I would like to gather some insight into whats possible. 1024 is a a lot - I want sharp filters. I tried 256 tap and a bit of optimsing in my code but still at 100k as would be expected!

Altera only has basic FIR IP built in but will look for others on their site. My FIR doesn't have a higher clock than the sample clock which does seem a bit of a waste as my sample rate is only 48kHz. I don't know of a FIR architecture that could make use of a fast clock without using a load of multiplexers to reduce multipliers and adders.

[Someone]

I don't know of a FIR architecture that could make use of a fast clock without using a load of multiplexers to reduce multipliers and adders.

The usual approach when you want to trade off area with throughput is to put the data into a buffer, the rams should take care of all the large multiplexing. One extreme end is fully combinatorial with 1 sample per clock throughput, and the other extreme end is the fully sequenced design which is blocking and takes n clocks to compute the result where n is the number of taps in the filter.

[langwadt]

1024 taps is a -LOT-...are you sure you need that many?  Does the Altera have built-in IP for FIRs?  I know Xilinx does, and you can trade off area for speed by feeding it a clock that's faster than the input data rate.  A couple of months ago I used it to implement a 144 tap LPF on an Artix-7.  625 kHz sample rate, 32-bit, dual channel, 40 MHz clock, and it takes up 14 of the 120 DSP slices on a 50k LE Artix-7 (negligible amount of other resources).

Thanks! I would like to gather some insight into whats possible. 1024 is a a lot - I want sharp filters. I tried 256 tap and a bit of optimsing in my code but still at 100k as would be expected!

Altera only has basic FIR IP built in but will look for others on their site. My FIR doesn't have a higher clock than the sample clock which does seem a bit of a waste as my sample rate is only 48kHz. I don't know of a FIR architecture that could make use of a fast clock without using a load of multiplexers to reduce multipliers and adders.

48kHz time 1024 taps is less than 50MHz. Two RAMs, one for data one for coefficients and a single multiplier accumulator and counter to do addressing should do it

[Boscoe]

1024 taps is a -LOT-...are you sure you need that many?  Does the Altera have built-in IP for FIRs?  I know Xilinx does, and you can trade off area for speed by feeding it a clock that's faster than the input data rate.  A couple of months ago I used it to implement a 144 tap LPF on an Artix-7.  625 kHz sample rate, 32-bit, dual channel, 40 MHz clock, and it takes up 14 of the 120 DSP slices on a 50k LE Artix-7 (negligible amount of other resources).

Thanks! I would like to gather some insight into whats possible. 1024 is a a lot - I want sharp filters. I tried 256 tap and a bit of optimsing in my code but still at 100k as would be expected!

Altera only has basic FIR IP built in but will look for others on their site. My FIR doesn't have a higher clock than the sample clock which does seem a bit of a waste as my sample rate is only 48kHz. I don't know of a FIR architecture that could make use of a fast clock without using a load of multiplexers to reduce multipliers and adders.

48kHz time 1024 taps is less than 50MHz. Two RAMs, one for data one for coefficients and a single multiplier accumulator and counter to do addressing should do it

Ahh yes this does make sense, thanks. Throws up some interesting challenges like writing and reading the input data in time. I like a challenge and I think this will be my route.