Fractional frequency dividers.

[firewalker]

What is the best way to implement a fractional frequency (<1 kHz) divider with a microcontroller (preferably an AVR). The fraction is 5/4.

Alexander.

[vealmike]

Write software.

Do you really mean 5/4ths? So the output is 1.25* higher in frequency that the original. Do you want to feed a square wave in, and get a square wave out at a different frequency, or is there more that you haven't told us.

Just one method would be to choose a micro with a much higher clock rate than the desired frequency. Measure the period of one (ore more) cycles of the input waveform. Use the measurement to adjust the timing of a software generated output waveform.

[firewalker]

Everything is 0-5 volts square pulses. The divider is 1.25. The output frequency will be Input/1.25.

I was thinking a simple frequency counter (counter with external clock and a .1 sec gate time) and a simple delay pin toggle.  Does it sound sane?

The application is for the conversion for the RPM pulses of 5 cylinder engine to an RPM meter of a 4 cylinder engine.

Alexander.

[agehall]

Does the number of cylinders affect how RPM is measured? Not sure I understand how this is done...

[firewalker]

Yes. It is an engine with a distributer for the high voltage. The PCM counts ignition coil pulses per revolution and feeds that info to the RPG gauge. The ignition coil pulses depends on the number of cylinders.

Alexander.

[NorthGuy]

Yes. It is an engine with a distributer for the high voltage. The PCM counts ignition coil pulses per revolution and feeds that info to the RPG gauge. The ignition coil pulses depends on the number of cylinders.

You can simply pass all the pulses through, but block every 5-th pulse.

[Kleinstein]

The simple way is pulse skipping. So leave out 1 out of 5 pulses.
The better, but more difficult way is a PLL to get 4 times the frequency and than divide by 2. One may be able to do this with logic ICs like an 4046 PLL and 2 dividers (e.g. HC74 + 4017). It is also possible to do the PLL in software, though it starts to get tricky at 10 kHz for an AVR.

[JPortici]

pulse skipping is the best, easies solution.
otherwise acquire the frequency and generate the new pulse with software DDS / Timers
at 9600 RPM, or 160 Hz, it's going to be 800Hz pulses in, 640Hz pulses out. Almost trivial.

I am doing a simillar thing with a PIC18 for airflow sensors. Using one timer i acquire the input frequency, using another timer i re-create the signal.
I have to compensate the reading for the interrupt routine entry latency, but once calibrated with a fixed value i can get to up to 8kHz with < 25Hz error, less if use different values for different frequency ranges (use the last acquisition to decide which compensation value to use). If the MCU wasn't doind a lot of other stuff i could probably get to > 10kHz but that's already outside the range of interest

[NorthGuy]

The better, but more difficult way is a PLL to get 4 times the frequency and than divide by 2.

PLL will not work when the input frequency is constantly changing (as the motor goes slower or faster).

[firewalker]

My bad. The frequency is less than 1 kHZ. I accidentally added a 0 to the first post.

Alexander.

[MT]

Use a Ghz clocked regular counter and pretend the resolution of that at 1Khz is sufficient to hit  close to your
fractional frequency. There are MCU's with these sort of things.

[Doctorandus_P]

Use a variant of the Bresenham line algorithm.

[lukewren]

My bad. The frequency is less than 1 kHZ. I accidentally added a 0 to the first post.

Alexander.

At sub 1 kHz you should be able to do pulse swallowing (pulse deletion) in software!

Sit in a loop, and for every pulse you see on your input, generate a corresponding pulse on the output -- except for every 5th pulse, where you generate nothing.

There is a general form (not just 5/4) where you accumulate a count of the fractional amount of pulses which should have been swallowed, and swallow a whole pulse when this accumulator goes above 1. This is the "variant of Bresenham's" an earlier poster mentioned.

[nfmax]

What is the best way to implement a fractional frequency (<1 kHz) divider with a microcontroller (preferably an AVR). The fraction is 5/4

We came up with a neat approach to this back in the 80's - https://patentimages.storage.googleapis.com/pdfs/e8707a5e10f639ed9f01/EP0236108B1.pdf

AFAIK all the patents will have expired by now.

[Kleinstein]

If the frequency does not change too fast a PLL can follow changes in the frequency. It is just that the loop filter must be fast enough and may thus not give you a very stable frequency. A mechanical system with a motor can not instantly change speed anyway. However it can get a little tricky if the frequency range is very large and may include a stand still.

Pulse skipping is definitely easy done with a µC at this low frequency. It is also possible to do a kind of PLL in software.

[nfmax]

Pulse skipping is definitely easy done with a µC at this low frequency. It is also possible to do a kind of PLL in software.

Our invention was a sort of feed-forward PLL. You measure the input period, and calculate the required frequency for an NCO to bring the accumulated phase error to zero, at the end of the next input period, if it is the same as the previous. The trick is in keeping track of all the sources of error so that they do not accumulate over multiple cycles. It can handle essentially arbitrary variations in input frequency, though it may take a while to bring the error back to zero.

[StillTrying]

Time the period between 2 input pulses, multiply it by 1.25, and use that as the period for the out pulses.
16 bit counts and 2us timing would do for ~8Hz to 1kHz+.

[Benta]

A 4-bit counter with decoded outputs can give you the following pulse pattern:

     11010010110100101101001011010010

Note that for 20 input clock pulses (black + red), you get 8 output pulses. Not equally, but regularly spaced, meaning you have a signal that's periodic and does not have DC bias.

Now we just need to double the input clock frequency and your 5/4 division is done. The simplest way is an XOR gate with a delay on one input.



For the counter? Well there are a lot of 4-bit counters around, but output decoding can be tedious. Personally, I'd cascade two 4022 Johnson counters and simply connect the outputs to a diode matrix (8 diodes needed).