GAL design software

[ianc]

Hi

I've been lurking for a while and have found the information posted here most useful.

I have a small project I'm working on which requires a small amount of glue logic and address/data latching which could be best achieved with some form of programmable logic. My thoughts were that I could use some small programmable devices e.g. 16V8 or 22V10 rather than discrete logic. I have a programmer (TL866A) which should program the devices but I'd like some guidance as to software for creating the .JED files to configure the devices.

Ideally I'd like something I could draw the schematic for the required circuit and the software would process the circuit and spit out a .jed file for the programmer. I suspect this is not an option on my tiny budget (I'm a hobbyist not a professional). So I would be willing to write logic equations if that is all the available (free) software can cope with.

My development environment is an ageing Core 2 duo laptop running Windows 10 at 1.75Ghz with 2GB of memory and a 250GB SSD so something fairly lightweight would be best.

Does anyone have any recommendations?

With thanks in advance

Ian

[capt bullshot]

Search for "PALASM". That's been the language / tool of choice when we used PAL / GAL back in the times ...

[voltsandjolts]

You might find it easier to use a small CPLD like Xilinx XC2C64A.
Small dev boards cheap on ebay (remnants of old PS3 hacking) and cheap programmers.
Easy schematic entry with Xilinx tools but you can do that with Lattice etc...

[technix]

Technically you can repurpose Atmel's free WinCUPL for things similar enough with Atmel's offerings - GAL16V8 or GAL22V10... I have yet to find a UNIX version of this.

[Bruce Abbott]

WinCUPL. It only works with equations, but that is the better way to do it. Drawing a schematic just means you have to  translate from logic to a circuit, then the GAL assembler has to convert it back again. You should treat the GAL as a 'black box' which performs the logical functions you need.

Here's an example taken from my Aquarius Micro-Expander project. It has address decoding for RAM and ROM, and I/O decoding to control a CH376 USB interface and set a latch which maps half the RAM over the ROM to emulate a game cartridge. I didn't even attempt to produce a schematic for this.

Code: [Select]

/* ***************** INPUT PINS ************************/
PIN  1   = A6      ; /* Z80 A6                         */         
PIN  2   = A7      ; /* Z80 A7                         */             
PIN  3   = A14     ; /* Z80 A14                        */             
PIN  4   = A15     ; /* Z80 A15                        */
PIN  5   = MREQ    ; /* Z80 /MREQ                      */
PIN  6   = RD      ; /* Z80 /RD                        */
PIN  7   = WR      ; /* Z80 /WR                        */
PIN  8   = IORQ    ; /* Z80 /IORQ                      */
PIN  9   = RESET   ; /* Z80 /RESET                     */

PIN  15  = LATR    ; /* Latch reset                    */ 
PIN  16  = A5      ; /* Z80 A5                         */

/* ***************** OUTPUT PINS ***********************/
PIN  19  = RA14    ; /* RAM A14                        */
PIN  18  = LATCH   ; /* Map upper RAM over ROM         */
PIN  17  = !RAME   ; /* 32k static RAM /CS             */

PIN  14  = !ROME   ; /* 16k ROM /CS                    */
PIN  13  = PRST    ; /* Peripheral RESET (active high) */
PIN  12  = !CH376  ; /* CH376 /CS                      */
 
RAME   = !MREQ&(!RD#!WR)&(((A15&!A14&!LATCH)#(!A15&A14))#(A15&A14&LATCH&!RD));
ROME   = !MREQ&!RD&A15&A14&!LATCH;
CH376  = !IORQ&(!RD#!WR)&!A7&A6;   
RA14   = A14&!(A15&LATCH);
LATCH  = LATR&((!IORQ&!WR&!A7&!A6)#LATCH);
PRST   = !RESET; 
The code structure is very simple. First you assign variable names to the pins, then describe the logic. Variables to the left of the '= ' sign are outputs, those on the right are inputs. WinCUPL takes care of the details.

You can also simulate your design if you want, but I found it was easier to just put the chip in a breadboard and attach dip switches and LEDs to the inputs and outputs.

Here's the compiler output listing for that code. At the end it draws an ASCII diagram of the chip with pin functions labeled. This is all you need to add your 'custom' logic  to your main schematic!

Code: [Select]

===============================================================================
                            Expanded Product Terms
===============================================================================

CH376 =>
    A6 & !A7 & IORQ & WR
  # A6 & !A7 & IORQ & RD

LATCH =>
    !A6 & !A7 & IORQ & !LATR & WR
  # LATCH & !LATR

PRST =>
    !RESET

RA14 =>
    A14 & !A15
  # A14 & !LATCH

RAME =>
    A14 & A15 & LATCH & MREQ & RD
  # A14 & !A15 & MREQ & RD
  # A14 & !A15 & MREQ & WR
  # !A14 & A15 & !LATCH & MREQ & WR
  # !A14 & A15 & !LATCH & MREQ & RD

ROME =>
    A14 & A15 & !LATCH & MREQ & RD

CH376.oe  =>
    1

LATCH.oe  =>
    1

LATR.oe  =>
    0

PRST.oe  =>
    1

RA14.oe  =>
    1

RAME.oe  =>
    1

ROME.oe  =>
    1


===============================================================================
                                 Symbol Table
===============================================================================

Pin Variable                                    Pterms   Max     Min   
Pol   Name              Ext     Pin     Type     Used   Pterms  Level   
--- --------            ---     ---     ----    ------  ------  -----   

    A5                          16       V        -       -       -     
    A6                          1        V        -       -       -     
    A7                          2        V        -       -       -     
    A14                         3        V        -       -       -     
    A15                         4        V        -       -       -     
 !  CH376                       12       V        2       7       1     
 !  IORQ                        8        V        -       -       -     
    LATCH                       18       V        2       7       1     
 !  LATR                        15       V        -       -       -     
 !  MREQ                        5        V        -       -       -     
    PRST                        13       V        1       7       1     
    RA14                        19       V        2       7       1     
 !  RAME                        17       V        5       7       1     
 !  RD                          6        V        -       -       -     
 !  RESET                       9        V        -       -       -     
 !  ROME                        14       V        1       7       1     
 !  WR                          7        V        -       -       -     
    CH376               oe      12       D        1       1       0     
    LATCH               oe      18       D        1       1       0     
    LATR                oe      15       D        1       1       0     
    PRST                oe      13       D        1       1       0     
    RA14                oe      19       D        1       1       0     
    RAME                oe      17       D        1       1       0     
    ROME                oe      14       D        1       1       0     


LEGEND    D : default variable         F : field      G : group
          I : intermediate variable    N : node       M : extended node
          U : undefined                V : variable   X : extended variable
          T : function


===============================================================================
                                   Fuse Plot
===============================================================================

Syn   02192 - Ac0   02193 -

Pin #19  02048  Pol -  02120  Ac1 -
 00000 --------------------------------
 00032 ----x----x----------------------
 00064 ----x--x------------------------
 00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #18  02049  Pol -  02121  Ac1 -
 00256 --------------------------------
 00288 -x-x--------------x--x---x------
 00320 ------x-----------x-------------
 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #17  02050  Pol x  02122  Ac1 -
 00512 --------------------------------
 00544 ----x-x-x----x---x--------------
 00576 ----x----x---x---x--------------
 00608 ----x----x---x-------x----------
 00640 -----x-xx----x-------x----------
 00672 -----x-xx----x---x--------------
 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #16  02051  Pol x  02123  Ac1 -
 00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #15  02052  Pol x  02124  Ac1 -
 01024 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01056 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #14  02053  Pol x  02125  Ac1 -
 01280 --------------------------------
 01312 ----x--xx----x---x--------------
 01344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #13  02054  Pol -  02126  Ac1 -
 01536 --------------------------------
 01568 ----------------------------x---
 01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #12  02055  Pol x  02127  Ac1 -
 01792 --------------------------------
 01824 -xx------------------x---x------
 01856 -xx--------------x-------x------
 01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


LEGEND    X : fuse not blown
          - : fuse blown

===============================================================================
                                 Chip Diagram
===============================================================================

                               ______________
                              |   Aqu_mem    |
                       A6 x---|1           20|---x Vcc                     
                       A7 x---|2           19|---x RA14                     
                      A14 x---|3           18|---x LATCH                   
                      A15 x---|4           17|---x !RAME                   
                    !MREQ x---|5           16|---x A5                       
                      !RD x---|6           15|---x !LATR                   
                      !WR x---|7           14|---x !ROME                   
                    !IORQ x---|8           13|---x PRST                     
                   !RESET x---|9           12|---x !CH376                   
                      GND x---|10          11|---x                         
                              |______________|

 

[technix]

I think the equation form used by WinCUPL is a good stepping stone from circuit diagrams to HDL. You can soon start wrapping your mind around the concept of describing hardware using code, and a few designs later you will start finding yourself getting larger and larger chunks of stuff done in FPGAs.

[TK]

I had good experience with PALASM running inside a DOSBOX.  The resulting JED file was used to program a GAL16V using TL866

[mikeselectricstuff]

It's maybe 20 years since I  used it, but From memory. WinCUPL is a lot more powerful than PALASM, as it does logic reduction and some state-machine stuff, whereas palasm is basically a textual representation of the device structure.
A bit like the  difference between C and assembler

[nctnico]

AFAIK PALASM can also do logic reduction and state machines but it has been 20 years since I last used it.

[TK]

I implemented a state machine for an HP 8714B IBASIC activation 2 months ago using PALASM:

https://www.eevblog.com/forum/testgear/how-to-activate-ibasic-on-vintage-hp-871xb-network-analyzers/msg1251274/#msg1251274

I think WinCUPL is more powerful, but I found PALASM easier to learn from zero.

[bobaruni]

Years ago, I used protel 99 SE.
I created a schematic and then used the compiler to create a jed file, was easy and worked very well.
Not sure if the newer Altium trial packages will allow this?

[danadak]

Depending on design you could always use PSOC.

http://www.cypress.com/documentation/application-notes/an62510-implementing-state-machines-psocr-3-psoc-4-and-psoc-5lp

Following URL, list of videos at bottom of page.

http://www.cypress.com/documentation/application-notes/an82156-psocr-3-psoc-4-and-psoc-5lp-designing-psoc-creatortm

Design can be done from schematic or Verilog. IDE fee. In fact one of the many
available GUI components in library is a LUT component.


Plus you get a GP processor, analog, DSP.....


Regards, Dana.

[martinator]

PALASM can also do logic reduction. I don't think it's as powerfull as Wincupl, but it can do state machines.  The simulator is better in WinCUPL as it's graphical. You lose track of which clock you are on in PALASM if you're doing a long simulation.

If you wanted to go really old school and create a schematic you could use DOS ORCAD with the PALASM plugin but it won't do devices as small as a GAL, you would have to use a MACH110 or similar. (I may have a win3.11 image for virtualbox with all that already installed.)

[xtech]

I'm creating designs for GAL chips in VHDL using free Lattice ispLevel Classic. But I'm not sure if there is possibility to draw logic on the schematics (probably no).

And remember - GAL22V10 are poorly supported in the tl866, 16v8 and 20v8 are ok

[thermistor-guy]

Hi

...

Ideally I'd like something I could draw the schematic for the required circuit and the software would process the circuit and spit out a .jed file for the programmer. I suspect this is not an option on my tiny budget (I'm a hobbyist not a professional). So I would be willing to write logic equations if that is all the available (free) software can cope with.

My development environment is an ageing Core 2 duo laptop running Windows 10 at 1.75Ghz with 2GB of memory and a 250GB SSD so something fairly lightweight would be best.

Does anyone have any recommendations?

With thanks in advance

Ian

My vote is for WinCUPL, freely available.

A comment on your laptop, if you are still using a 32-bit processor. I still make use of a 10yo laptop with similar specs to yours, but I upgraded it with a T7600 64-bit processor so I could run Linux.

https://ark.intel.com/products/27257/Intel-Core2-Duo-Processor-T7600-4M-Cache-2_33-GHz-667-MHz-FSB
https://www.amazon.com/Intel-T7600-2-33Ghz-Fsb667Mhz-Fcpga6/dp/B000I77VES

You can still get T7600s from Amazon and other sellers. Check that you are running the latest BIOS for your laptop before upgrading, if you decide to do that.

[technix]

Hi

I've been lurking for a while and have found the information posted here most useful.

I have a small project I'm working on which requires a small amount of glue logic and address/data latching which could be best achieved with some form of programmable logic. My thoughts were that I could use some small programmable devices e.g. 16V8 or 22V10 rather than discrete logic. I have a programmer (TL866A) which should program the devices but I'd like some guidance as to software for creating the .JED files to configure the devices.

Ideally I'd like something I could draw the schematic for the required circuit and the software would process the circuit and spit out a .jed file for the programmer. I suspect this is not an option on my tiny budget (I'm a hobbyist not a professional). So I would be willing to write logic equations if that is all the available (free) software can cope with.

My development environment is an ageing Core 2 duo laptop running Windows 10 at 1.75Ghz with 2GB of memory and a 250GB SSD so something fairly lightweight would be best.

Does anyone have any recommendations?

With thanks in advance

Ian

I have a spare T7400 (slightly slower than T7600 at 2.17GHz instead of 2.33GHz, but otherwise the same) I can sell you that if you want to.

[jmarkwolf]

Years ago, I used protel 99 SE.
I created a schematic and then used the compiler to create a jed file, was easy and worked very well.
Not sure if the newer Altium trial packages will allow this?

I also did this for many years. Worked great.

Still have bundles of tubes of GAL's!