Getting started with FPGA

[NorthGuy]

So for beginners learning VHDL is a pure waste of time because they invest time into dying technological dinosaur. Their time will be much better spent learning SystemVerilog.

I don't think so. When you get proficient with any HDL, switching the language is not such a big deal.

[rstofer]

Despite all the more recent "technically better" programming languages, C  is still rather popular...
Any language that has been around for 30 years isn't going away any time soon.

The first K&R C Language book came out in '78 so C is maybe about 40 years old and is still used for all embedded programming and most OS code (Linux kernel, most of Windows, etc).

Fortran was released in '57 so it's about 60 years old and COBOL came out around '60 so it's about 57 years old.  There's a lot of Fortran use out in the wild, COBOL is kind of a niche thing.

Those 3 languages are likely to be around forever.  Every other language is just passing through (PL/I, Pascal, Modula, Algol, etc).  Anybody remember PL/I?  I used it to write an 8080 assembler in grad school.  I struggled with the transition from Fortran to PL/I but, in retrospect, I should have spent more time with the language.  There was even a version for CP/M (which I still have).  Think about it!  PL/I on an 8 bit 64k machine.

[nctnico]

Agreed and recent survey shows this as well: https://groups.google.com/forum/#!topic/comp.arch.fpga/fN6nsmi--u0

Hardware engineers are some of the most stubborn people I ever interacted with, and often this stubbornness is to their peril. But even they are slowly realizing advantages of SystemVerilog/SystemC for verification, and only continue using VHDL because of their stubbornness (as it doesn't make any technical sense whatsoever). But obviously this is only a temporary state of affairs, and no matter what some people want, single language is always better than multiple. So for beginners learning VHDL is a pure waste of time because they invest time into dying technological dinosaur. Their time will be much better spent learning SystemVerilog.
And I know VHDL folks over here will keep arguing until cows fly, but the history has plenty of examples of what happens to those who try to go against technological progress. Unless they want to share their fate, they will have to adapt.

That is wishfull thinking. To me Verilog looks like completely unstructured gibberish long before I even started working on FPGAs. SystemVerilog is much the same so even with VHDL hacked into Verilog (what they now call SystemVerilog) I wouldn't start using SystemVerilog. I'm sure I'm not the only one.

[SiliconWizard]

Nice flame war guys.
And the author is probably now even more confused than when he first created the topic. 

[NorthGuy]

Anybody remember PL/I?

I do. You don't need to declare variables. Anything which starts from I to N automatically becomes integer. It's a nice feature when you work with punch cards.

Just pure coincidence, but most of the integers I use in C start from a letter between I and N

[DocOptics]

I had a requirement about 5 years ago to get into FPGA design.  Here is how I did it from zero to doing it as part of my professional life.

Which FPGA board?
Started with a DE0-Nano board.  It was cheap and has some on-board bits a pieces (LEDs, switches...)  That meant I started down the route of the Altera toolchain.  A month or two into learning (which was helped by the Altera website which had loads of video tutorials and documentation about FPGA design) the requirement changes as the company policy is to use Xilinx hardware...

2nd board was a Papilio One (Xilinx Spartan 3).  Used this to learn how the Xilinx toolchain works.  Has fewer on-board bits, but lots of I/O headers (0.1 inch!) so interfacing my own hardware (more LEDs and swithces) to it was easy.

At this point the professional requirements starting kicking in, so my next couple of boards were:
Avnet Spartan 6 microboard.  Cheap.  Has Ethernet and a few 0.1 inch headers.  Had the added advantage that at the time the Xilinx license that comes with it also unlocks the full ISIM simulator and ChipScope. (It might still do - haven't looked)  Learnt all about Ethernet MACs, and encoding for data transmission.

SP605 Development Kit (Spartan 6).  At the time expensive.  Used it to learn all about the horrors of using SDRAM in a design.  My main goto development board at the moment.

Recently I have moved onto AC701 development boards, as Xilinx don't seem interested in updating ISE (series 6 FPGAs), and it is all Vivado (series 7+) with them now.

Which language?
Asking this is always guaranteed to start a religious war.
I selected a language by using both VHDL and Verilog for a few weeks each, and seeing which one clicked in my brain quicker.  Try writing the blinky LED in both see which you prefer.  Both are equally weird languages in their own way.
I now use Verilog (as ISE doesn't support SystemVerilog) but I am migrating to SystemVerilog as Vivado supports it.  As a longtime C++ user I prefered the syntax of Verilog.
Whichever language you choose, repeat "I am designing hardware, not software" until it sticks.

To simulate or not to simulate?
Depends what you are doing.  To start off with I found not simulating fine; I was only building small designs that took a few seconds to run through the tools (and ISIM evaluation version has some limitations on design size).  As I got into building large systems the times got longer it become easier to write testbenches and simulate it.  Once I had a decent simulator and built up my library of HDL I now tend to simulate most things first.  My largest designs now take about an hour to simulate, but take about 3-4 hours to synthesize fully - time is money...

Hope this clarifies your thinking

Gavin

[nctnico]

Whichever language you choose, repeat "I am designing hardware, not software" until it sticks.

Definitely no to that! It will result into long winded code because you are basically writing netlists. It is kinda like writing a program in C and use inline assembler. Xilinx (for example) has good documentation on how the synthesizer converts HDL into FPGA building blocks efficiently. THAT is what you need to learn because that allows you to do a lot with only a few lines of code.

I find a lot of VHDL examples use an extremely long winded way of writing and they could easely be replaced with something shorter and scalable as a bonus. Sure if you need speed then go bare metal but it is similar to C versus assembly. 99% of the FPGA designs don't need speed. Overall I have the feeling a lot of FPGA designers are still in the 'assembler' stage and not confident enough to let the synthesizer do the work for them.

In the end you aren't describing hardware at all but logical equations / functions!

[rstofer]

Nice flame war guys.
And the author is probably now even more confused than when he first created the topic. 

Why should he be any different than the rest of us?  We're all going to tout the language we use and, in doing so, perhaps we give examples of why (didn't happen in this case).  In so doing, perhaps we influence a decision that actually helps.

In the end, it's just an opinion.  More often than not, for professionals, there is no choice.  The company chose long ago.

Harris and Harris in "Digital Design and Computer Architecture - ARM Edition" and in their earlier MIPS edition present SystemVelilog and VHDL side by side for all of their code examples.  This might be an ideal way to compare the languages on a real project.  Let's face it, blinking LEDs don't really provide an opportunity to compare much of anything.

[NorthGuy]

Recently I have moved onto AC701 development boards, as Xilinx don't seem interested in updating ISE (series 6 FPGAs), and it is all Vivado (series 7+) with them now.

ISE supports some of the Artix-7 chips.

ISE also has XDL, which is analogous to assembler language for MCUs, but I don't think anyone actually uses it.

[suicidaleggroll]

I think several people here are forgetting what it's like to be new to FPGAs.  So much of the HDL languages is only valid in simulation, trying to start out with simulation is absolutely the wrong way to go about it in my opinion.  Writing synthesizable code AND a simulation test bench for it is like trying to learn two languages at once.  I found it much simpler when I was first starting out to focus solely on synthesizable code, debugging on actual hardware.  Only after learning the ins and outs of the language did I start exploring simulation, and all of the added syntax and options that come with it.  I tried doing simulation at first, but I just kept getting thrown by what syntax was allowed where, it's too much for somebody just starting out in my opinion.  Not to mention the fact that debugging on actual hardware is far more rewarding and encouraging for someone starting out than just some virtual bit flips on a trace on a screen.

[nctnico]

I tend to agree. I'm only using simulation on FPGA designs which take very long to 'compile' and even then I only simulate the part I'm adding/changing.

[DocOptics]

Recently I have moved onto AC701 development boards, as Xilinx don't seem interested in updating ISE (series 6 FPGAs), and it is all Vivado (series 7+) with them now.

ISE supports some of the Artix-7 chips.

ISE also has XDL, which is analogous to assembler language for MCUs, but I don't think anyone actually uses it.

Thanks.  I know it supports Zynq, but didn't realise it supported some Artix 7 FPGAs.  It is still dead in the eyes of Xilinx..

Gavin

[DocOptics]

Whichever language you choose, repeat "I am designing hardware, not software" until it sticks.

Definitely no to that! It will result into long winded code because you are basically writing netlists. It is kinda like writing a program in C and use inline assembler. Xilinx (for example) has good documentation on how the synthesizer converts HDL into FPGA building blocks efficiently. THAT is what you need to learn because that allows you to do a lot with only a few lines of code.

I find a lot of VHDL examples use an extremely long winded way of writing and they could easely be replaced with something shorter and scalable as a bonus. Sure if you need speed then go bare metal but it is similar to C versus assembly. 99% of the FPGA designs don't need speed. Overall I have the feeling a lot of FPGA designers are still in the 'assembler' stage and not confident enough to let the synthesizer do the work for them.

In the end you aren't describing hardware at all but logical equations / functions!

Let me expand on that comment.

It is really getting into the correct mindset.  Often I have seen beginners trying to write programs (a sequential set of instructions) in HDL.  This leads down a bad path.  The designer should be thinking "all this happens simultaneously".

By all means use the higher level abstractions your favourite HDL provides; who wants to write more than they need to?

Gavin

[nctnico]

Parallel versus sequential is definitely something you need to wrap your head around. What doesn't help with that is that the order of statements does matter in HDL as well and assignments can be silently ignored by the synthesizer. For clarity it would be nicer to allow only one assignment.

[SiliconWizard]

Why should he be any different than the rest of us?  We're all going to tout the language we use and, in doing so, perhaps we give examples of why (didn't happen in this case).  In so doing, perhaps we influence a decision that actually helps.

This was clearly getting to the typical language flame war without any real added value. As you just said, giving articulate arguments could have helped, but it didn't happen. Merely stating that one is just better and the other is outdated or crappish leads to nowhere. We have seen that constantly happening on forums and newsgroups about C vs C++ vs Java vs you-name-it, VHDL vs Verilog vs SystemVerilog vs SystemC and it usually leads to nowhere. Many people have predicted (and will predict) the demise of this and that just based on how long it has existed, and the newcomer taking over the whole world, and it has never proven to be right until now. This is moot, all of these languages are widely in use today and each for good reasons. (Although SystemC is not that widely used.)

In the end, it's just an opinion.

Yes, so it's best to state it and hopefully with a rationale, so that gives something to think about. Raw opinions without rationales rarely help people making informed decisions.

More often than not, for professionals, there is no choice.  The company chose long ago.

That's right. From an historical point of view, VHDL has been prevalent in Europe and Verilog in the US. So that just adds up to the probablity of flame wars, even more so than with other languages.
Of course, there are now many exceptions to this rule. But this is something to keep in mind.

As others have said, language-wise, the best approach would be for a newbie to take a look at the various options (excluding the very 'exotic' ones) and see what best clicks for a start. The real point being to learn HDLs and how to develop digital designs more so than learning a specific language. Then if there is ever a specific company that he/she would really be interested in working at, getting to know what HDL they use would help deciding, at least for the short term.

As for me, I find VHDL much more readable, capable and maintainable than Verilog. Some find it verbose, that's something to consider. (And I've been using C as my main programming language for a long time, so saying that C developers are more inclined towards Verilog is not necessarily true at all.) I don't know much of SystemVerilog, so I can't really compare, but as I reckon, it's mostly Verilog with extensions for the RTL part, so for beginners, it probably won't make much of a difference. It's much more capable for verification though, but I've never really tried. You can also do very decent verification with VHDL. One other point to consider is that SystemVerilog is still partially/or unsupported in many existing tools.

Other points that come to mind: there are many processor cores that are written in Verilog, so that would be useful to master Verilog if you intend to get into this business or at least intend to use one in some project. On another level, I think VHDL is still the language of choice in system-critical designs, including the military, in a lot of countries.

But again, what's important for a beginner is grasping the concepts of HDLs and digital design.

And finally, for a more practical approach, since the author is interested in the "MiSTer" board, there are several example projects for this board in the repo that are written in Verilog. Something to think about.

[rx8pilot]

Did anyone mention the Nandland Go Board?

Simple intro to FPGA development without much distraction from fancy advanced stuff. Cheap enough that there is no tears when you outgrow it, yet enough toys to dig your heals into FPGA world.

Russel has some well considered and plentiful YT videos that a beginner can follow along. Seems like a great place to start.

https://www.youtube.com/channel/UCsdA-aNqtMA1_2T15aXePWw
http://nandland.com/

[mac.6]

and supported by Icestorm, so less hassle working trough the software itself as it is relatively straightforward (you just need to learn how to instantiate special IO block and PLL in the code).

[mikeselectricstuff]

Video on VHDL Vs. Verilog with some stats :

[mac.6]

If amateur, choose one and be a dick about it. If professional then you need both and systemVerilog also.

So in the end it doesn't matter really...

[james_s]

I've observed far more rampant elitism in the FPGA development community than anywhere else in my hobbies. Perhaps the only place I've been with a worst case of that is the hardcore Linux guys which unfortunately drives many less technical people away from what is otherwise a great OS. I suppose it's unavoidable when you have such a small group of people working with something esoteric that is by any measure difficult to learn. My goal is to expand this community and get as many people playing with FPGAs as possible, even if most of them never approach a professional level.

When it comes to languages, the verbosity is one of the things I like about VHDL and as someone who thinks in a very literal way it meshes well with the way my mind works. I can type faster than I can think in many cases so having to type more is not really an issue. Having started out in VHDL and gotten the hang of things I later found I was able to pick up and understand Verilog relatively easily however previously it looked to me as someone else here said, incomprehensible gibberish, like trying to read my mother's shorthand cursive notes. Liberal use of comments is important in any language but even more so with Verilog.

Whatever the case, starting out is very difficult, or was for me. It took me about 2 years of on and off tinkering before something finally clicked and I got to where I could write HDL from scratch and it would more or less work in most cases after fixing a few typos. I initially started playing with the simulator but found it boring and abstract, making actual hardware *do* something is far more engaging, then once I had the basics down I went back and revisited simulation. Even so a lot of the projects I do are simple enough that it's unnecessary, or major blocks like softcore CPUs and ASICs have already been developed and simulated by someone else so I don't need to reinvent the wheel.

[NivagSwerdna]

I've decided to get slightly side tracked.... thought I would play with 22LV10 whilst I get my Quartus II issues sorted.

[nctnico]

If amateur, choose one and be a dick about it. If professional then you need both and systemVerilog also.

So in the end it doesn't matter really...

I'd be carefull with these kind of statements. In my experience it takes time to master a language well enough to take full advantage of it. Learn 3 languages and you triple that time. What you are proposing is like learning all the ins&outs of C, Java and Pascal and their libraries.
Besides that I've been working with FPGAs for nearly 20 years and never needed anything else other than VHDL.

[NorthGuy]

So in the end it doesn't matter really...

...

Besides that I've been working with FPGAs for nearly 20 years and never needed anything else other than VHDL.

Do you mean, if that was Verilog (instead of VHDL), it would make huge difference in your life?

<edit>Voulez-vous dire, si c'était Verilog (au lieu de VHDL), cela ferait une énorme différence dans votre vie?

[james_s]

Anything you can describe in VHDL can be described in Verilog and vice versa. It's not like a traditional programming language where you see large variations in what is possible or in the performance of the finished product. No matter which HDL you use, the end result in the FPGA fabric is largely the same. Now there are caveats of course, it's possible to write code which will synthesize as a giant mess, and there are certainly optimizations that can be done but it's not the same as a traditional programming language and it applies to any HDL. Making your code more compact has no direct bearing on he ultimate result.

I don't understand the religious war, in the end it doesn't matter. Most of us hobbyists working with FPGAs have no intention of doing it for a living, and most of us are not building anything very complex, for me if it takes 10 minutes to synthesize that's a *really* big project. Spend some time playing with the languages available and pick the one you like the best, resting assured that you can achieve exactly the same result as someone else using a different language. The language itself is only a small part of the equation anyway, the more important aspect is the design itself that you're trying to describe.

[rx8pilot]

If amateur, choose one and be a dick about it. If professional then you need both and systemVerilog also.

So in the end it doesn't matter really...

I'd be carefull with these kind of statements. In my experience it takes time to master a language well enough to take full advantage of it. Learn 3 languages and you triple that time. What you are proposing is like learning all the ins&outs of C, Java and Pascal and their libraries.
Besides that I've been working with FPGAs for nearly 20 years and never needed anything else other than VHDL.

True.....choosing wisely at the beginning is very important since time is not unlimited.