How do your wife ISR look like?
Pretty much the wife ISR is the highest priority and I will soft lock and starve any other tasks until I'm done handling that interrupt request.
I used to just set a flag on the handler so I could use decent time slices for the task but that cause segmentation faults requiring to do the full task when the wife ISR is raised and don't let any other task progress regardless on how many cores are available.
Other than that she works on Sunday so I can pull the pin high to avoid that interrupt to be triggered since it uses negative logic
Been working on it but did hit a problem.
Just doing the PWM for now for the HSync and VSync it looks like something broke on the newer PWM modules V3.30 and I was getting this for HSync (Yellow trace) and VSync (Blue trace).
Nothing seemed to work right and after a lot of head scratching I went to an older version of the PWM module V3.0 and now I'm getting more or less what I was expecting. (not changing a thing other than the version of the module)
Note the 10.0V, that's because I forgot to change the channels to 1X and I'm using a VGA to BNC cable to capture the signals, like this picture:
White cable is HSync, Black is VSync. Connecting with a T connector and 75 Ohm terminators as required by VGA (and video in general).
Edit, HSync and VSync are TTL levels, so I guess I didn't need to terminate them. RGB signals on the other hand do need to be 75 Ohm terminated.
But I won't start the thread until I have a good summary and 1st part with an explanation on how it will progress. I'm working on the write up now and will do a post with reserved post to expand each step.
Also I will open a support ticket with Cypress with the first example to see what has changed from V3.0 to V3.10 and on (Tried 3.30, 3.20, 3.10 and they all where misbehaving for this use and downgrading all the way to V3.0 fixes the problem).