My opinion, for what it's worth, is that it's pushing it to consider a processor is Harvard just because it has a prefetch queue (all six bytes of it). The instructions still come from the the same bus that is shared with the data.
At the end of the day it ends up being little more than a subjective academic exercise putting different processors into different buckets such as RISC/CISC or von Neumann/Harvard. In practice when implementing a solution on a given device, what notional arbitrary bucket they might or might not be in is irrelevant: a more detailed and granular understanding is of far more relevance.