So it might be called a modified Harvard architecture.
and that is how intel refers to it as well. Actually the original processors were micro-coded. THat micro code sits in a dedicated rom with its own address and data bus , not accessible to data.
As for an 8086 beeing able to boot : that is a simple matter of how the memory management is set up. you can do the same with an 8051. you can store a bootloader in rom, copy it into ram at startup , swap the banks around , reset the cpu and restart from ram. There is all kinds of trickery you can do.
None of that trickery defines the processor being one or the other.
A harvard machine uses different pathways for code and data in the core. a von neumann does not. This saves pathways and 'real estate'. drawback : when fetching data the bus is in use. in a Harvard processor the processor can alreay prefetch the next instruction ( provided the busses are split on the package as well.
on an 8051 (optimised single or two cycle architecture running from internal rom) , where there is internal memory the core actually can do that. They pre-fetch the next instruction while data transport is happening to/from external ram.So on the first clokctick after the last XRAM operation the instruction is ready to go. the bus cycle there has already completed.
If you retain the harvard setup throughout the architecture of the machine you end up with something that is much easier to debug.
1) data can never overwrite executable code. so buffer overflows , wrong pointers etc cannot corrupt the code.
2) Stack overflows cannot corrupt executable code
3) when looking at a memory dump you never have to wonder what you are looking at. this makes tracing program execution a lot easier.
4) when building a system you do not need to worry about memory layout and mapping. since data and code live in separate spaces you have both a data pointer and a code pointer. both start at zero. in von neumann one needs to be mapped after the other. if your code increases in size all the data needs to shift up (or down if code size shrinks )
5) in the 'olden days' this partitioning was easy. code goes into rom , the rest into ram. This makes the compilers easiers, the chip layout easier (for rommable devices )
6) when using memory backup ram or eeprom for nonvolatile storage you can overwrite the rom without having to worry about shifting stuff around.
7) the above is the reason why, in von neumanns they grow stack space and data from topmem down , and code from bottom up so they don't have to worry about 'overlapping'. in harvard both map from 0 up.
you can hotboot van neumanns without problems. Every ADSL modem (both sides of the wire) in the world does that , and i wrote the bootloader for that (the standard on how they load code) the principle is simple.
At a very high memory address there is a bootloader code. The processors logic is setup that, when a cold start reset happens the CPTR is set to that address and the loader executes. The loader checks the flash area for a valid 'signature' (0x55aa) telling him there is a valid program image present.
If the signature is there the bootloader initializes the sdram controller and starts copying the flash to sdram at absolute address 0. When done, a write-only register in the Reset system is set to indicate that we have successfully loaded the system image. Then a warm start is executed: The processor is reset again, but this time the CPTR is set to 0 (that write only bit indicates to preload the CPTR with 0 to run the code or preload with the 0xFFF00000 address to run the bootloader in rom. The rest system also alters the bus timing so the processor runs at low clockspeed from flash and high clockspeed form sdram ( the rom and flash have much slower bus timing than the ram)
if there is no signature present the bootloader considers the system image missing , sets up a tftp-like connection over the datapipe and requests firmware from the host system. The datapipe can be switched to a simple serial port by pulling down an i/o pin. this is used to load the FLASH in circuit during the board test procedure. IF a valid code image has been receive , the checksums are correct then the signature is written.
if a request comes from the system firmware to perform a firmware update then a routine is activated , in the firmware , to erase the signature field , and perform a warm start. Even at a warm start the signature is checked.
coldstart : boot from FFFF0000 check signature . no signature : loader mode , signature : warm start
warm start : no signature -> enter bootloader , signature : set cptr to zero and go.
This was on an ARM 7. the bootloader uses a simple ASCII transport mechanism you basically upload a intel HEX file with the system image. the loader has single character control commands
R = reset
W = warm start
O = offset ( sets the CPTR to this address )
U = upload
and there were a few others. i don;t remeber the complete set. the loader was just short of 800 bytes and sits in hard rom inside the asic.