help! how to make a nsc800 computer?

[Bruce Abbott]

When I read that, You are saying you have built all the test equipment that you use! If true then great, but double standards are bad.

The very first piece of test equipment I had was a multimeter made from a 500uA movement and a bunch of resistors.  In 1978 I built a multi-function meter with DC Volts, kHz, milliseconds, nF and uF ranges (shown below) all to my own design. This meter is still in use today. I also built 3 oscilloscopes from scratch (the first one used a 1 inch radar tube and fitted into a briefcase along with the meter and other tools).  No double standards here!

The advantage of designing and building your own tools is that you know exactly how they work and what their limitations are. This knowledge also helps when using commercial equipment.
 

True but no eeprom programmer needed so what is saved can buy a Z80
And the NSC800 can be a small step in the future after learning the basics.

This thread is about building an NSC800 computer. ali6x944 could just make an exact duplicate of the Hackaday Z80/ATmega32 project instead, but what would be the fun in that?

Break a big project down in to small simple steps that you can test. After a time you have that big project.

I agree. That is why I recommended getting an EEPROM programmer. He already has the NSC800 working, next step is to replace the nop generator with a ROM. Then he can burn simple programs into the ROM and verify its operation, add a RAM chip, then an SIO chip - gradually building up a complete computer.

The programmer may also be useful for other projects. The Minipro also does GALs (16V8, 22V10) which are a good introduction to programmable logic.
   

Here one step is Wiring, it has to be perfect

Agreed. My first step in building a design is to print out the schematic. After doing the wiring I then buzz it out with the continuity tester, marking each connection on the schematic until they are all verified. I also power the board up before installing the chips and check that all the voltages are correct. Saves much heartache!

[ali6x944]

hi again,
sorry for not replying for a while now, I was improving the NSC800 testing circuit and I added the following:
1x 74LS374 for de-multiplexing the lower 8-bits of the address bus
 and the clock stop circuit from page 15 of the NSC800 datasheet with a 4MHz crystal
the following image is for these signals:
CLOCK (in yellow)
ALE (in cyan/light blue)
/RFSH (in purple)
/RD (in blue/dark blue)
https://drive.google.com/file/d/0B5vW-k7HbsL4TmFwbXFYZkpGUjg/view?usp=sharing
https://drive.google.com/file/d/0B5vW-k7HbsL4Rkd3NWE3dVBHcnM/view?usp=sharing
note: see page 9,15,16,17,18 and 19 of the NSC800 for reference:
https://drive.google.com/file/d/0B5vW-k7HbsL4S2ZmQTVzaTNXTjA/view?usp=sharing

[ali6x944]

photos of the circuit on the breadboard:
https://drive.google.com/file/d/0B5vW-k7HbsL4b2RvX3NuanJaVjA/view?usp=sharing
https://drive.google.com/file/d/0B5vW-k7HbsL4LTNObktlckhPd1U/view?usp=sharing
https://drive.google.com/file/d/0B5vW-k7HbsL4UTZ1cWh4cHR4UjQ/view?usp=sharing
https://drive.google.com/file/d/0B5vW-k7HbsL4ZG9TTlN3UmN4Tk0/view?usp=sharing

[C]

hi again,
sorry for not replying for a while now, I was improving the NSC800 testing circuit and I added the following:
1x 74LS374 for de-multiplexing the lower 8-bits of the address bus

74LS374
The eight flip-flops of the DM54/74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were set up at the
D inputs.

74LS373
The eight latches of the DM54/74LS373 are transparent
D-type latches meaning that while the enable (G) is high the
Q outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.

NSC800 page 8
ALE
Address Latch Enable (ALE): Active high. ALE is active
only during the T1 state of any M cycle and also T3 state of
the M1 cycle. The high to low transition of ALE indicates
that a valid memory, I/O or refresh address is available on
the AD(0 –7) lines.

NSC800 Page 70
shows it

What is wrong here with the 74LS374

Datasheet
http://ecee.colorado.edu/~mcclurel/dm74ls373.pdf

[ali6x944]

I'm having a couple of problems regarding the clock circuit and the AD0-AD7.
the output at A0-A7 is horribly distorted, I don't know what is the cause and will try my best to to figure what on earth is happening!?
and thanks for all replies   

[ali6x944]

I think I have another one on me, I will replace the chip just give me a couple of minutes...

[C]

This is just about ALE, and on paper 

ALE
For now do not worry about the scope

Just read my post and think logically.
When you know what this change of chips does then you might think of what problems it could create.

[ali6x944]

unfortunately, I don't have 74LS373...
but I have ONLY 74LS273  and 74LS374....

[C]

Not trying to be mean.
For now it does not matter if you have a 7474LS373 or not

What does a change of a logic chip from 74LS373 to 74LS374 do?

What changes would this make to the NSC800

It is a THINK problem.

[ali6x944]

ohh! I got ur point!!
the 74LS374 is edge triggered clock while what I really needed was state triggering clock of the 74LS373...
so even the 74ls273 would not work...

[C]

BINGO

Now go a step forward what happens with lower address bus with the two different chips?

[C]

ohh! I got ur point!!
the 74LS374 is edge triggered clock while what I really needed was state triggering clock of the 74LS373...
so even the 74ls273 would not work...

Not quite correct here.
You could have a chip that triggered on a falling clock trigger.
What would be the difference between a falling clock trigger and theLS373?

The problem
1. You have a positive edge triggered chip ( 74LS374 )
2. You have a transparent latch with data latched on negative edge(74LS373).
3. You have a  negative edge triggered chip like 74LS374 but negative edge in place of positive edge.

All will effect what is on A0-A7, What are the changes to A0-A7 using the three different chips?

ohh! I got ur point!!
the 74LS374 is edge triggered clock while what I really needed was state triggering clock of the 74LS373...
so even the 74ls273 would not work...

Not quite correct here.
You could have a chip that triggered on a falling clock trigger.
What would be the difference between a falling clock trigger and the 74LS373?

that A0-A7 is load on the edge of the ALE signal in 74LS374.
conversely the A0-A7 it is loaded when the ALE signal goes high meaning not on the transition in 74LS374.

Close
What happens for #2 if the input is changing?

[ali6x944]

ohh! I got ur point!!
the 74LS374 is edge triggered clock while what I really needed was state triggering clock of the 74LS373...
so even the 74ls273 would not work...

Not quite correct here.
You could have a chip that triggered on a falling clock trigger.
What would be the difference between a falling clock trigger and the 74LS373?

that A0-A7 is load on the edge of the ALE signal in 74LS374.
conversely the A0-A7 it is loaded when the ALE signal goes high meaning not on the transition in 74LS374.

[C]

If you use a 74LS374
  Input is captured on positive edge, output sees no more changes. If input is still changeing then output is wrong.

If you use a 74LS373
  Input starts showing on output when level is high and follows all changes to input.  Changes stop  when low.

The #3
  You do not see input on output until you have the negative edge.

At high speed with NSC800 a 74LS374 can give an invalid A0-A7 address.
The 74LS373 will pass the changing address to down stream devices giving a little more time to these devices if address is stable. Change stops on ALE going low which is when NSC800 says A0-A7 should be stable.

The #3 would work fine also, but you would not have the extra time that A0-A7 might be stable for down stream devices.

Now think how a simple change like a 74LS373 being replaced by a 74LS374 messes with you.
Could be a very hard to find problem. Might not happen but once in a 1000 address requests.


 

[ali6x944]

If you use a 74LS374
  Input is captured on positive edge, output sees no more changes. If input is still changeing then output is wrong.

If you use a 74LS373
  Input starts showing on output when level is high and follows all changes to input.  Changes stop  when low.

The #3
  You do not see input on output until you have the negative edge.

At high speed with NSC800 a 74LS374 can give an invalid A0-A7 address.
The 74LS373 will pass the changing address to down stream devices giving a little more time to these devices if address is stable. Change stops on ALE going low which is when NSC800 says A0-A7 should be stable.

The #3 would work fine also, but you would not have the extra time that A0-A7 might be stable for down stream devices.

Now think how a simple change like a 74LS373 being replaced by a 74LS374 messes with you.
Could be a very hard to find problem. Might not happen but once in a 1000 address requests.


 

mmmmm.....
so to fix the problem that the 74LS374 makes, I need to somehow shift the trigger from rising edge to a falling edge...
by using 74ls04 inverting the ALE.
I was also thinking of connecting the 74ls374 clock to the clock of the NSC800 and the output enable to the ALE to because the OE is not edge triggared...

[C]

First, When you look at the NCS800 and it's timing diagrams, the ALE signal timming is built for some chip like 74ls373. Any change needs to look at all the details.
The ALE signal is also a time reference for other signals.

Looks like you are starting to think.
An inverter connected to clock input 74ls374 does change the edge.
You have a slow #3


What else happens when you do just this much?
Everything takes time. The inverter delays the change 74ls374 clock signal.
You are now capturing A0-A7 at a later time. Is A0-A7 still valid at this time?
You have also reduced the time A0-A7 is valid down stream from 74ls374.

At some point as clock speed increases the extra delay breaks the logic. If this happens at a higher clock then can be used then it could be ok.
It is ALL ABOUT TIME.
In some places while the logic of a 74ls374 is correct you might need to use something faster to get the TIME to work.

Do not see cpu clock doing you any good. To match up with other systems, the ALE latch is a problem
For something looking for Z80 type then OE needs to set output to tri-state during DMA and RESET. Z80 DMA needs all 16 address lines.
For something looking for 8085 then it might be only RESET.

The NSC800 is a mess.
Z80 machine code should work but this is not a guarantee as code has to work with hardware at some point.
While the interface of this chip looks like an 8085, it might not be due to a timing change or signal difference. 8085 chips might work, might not do to logic & timing changes.
Z80 chips like SIO will not work to full function. And only testing each chip will give a guess if remaining parts of chip will function.
Being able to run Z80 code does not mean that a Z80 SIO will function. You should be able to already see that some parts of SIO will not work. The SIO can read the instructions the Z80 is reading due to M1, Z80 has a return from interrupt instruction.
Interrupt ack is also created inside SIO which is used to define when to put an interrupt vector on bus.
There is a reason that  ZILOG introduced new versions SIO when introducing faster Z80 CPU's.
later in Z80's life time a whole new chip replaced the SIO.


 

[C]

For slow speed the 74ls374 with inverter should work.
Replace with a 74ls373 as soon as you can get one.

There are other logic families that you could use in place of LS

You said you have a 74ls273
You could replace grant's logic on his CP/M version that insures that ROM is in memory on cold boot with this chip.
The extra 7 could be used in the future change memory map or other functions.

[Bruce Abbott]

An inverter connected to clock input 74ls374 does change the edge.
You have a slow #3


What else happens when you do just this much?
Everything takes time. The inverter delays the change 74ls374 clock signal.
You are now capturing A0-A7 at a later time. Is A0-A7 still valid at this time?
You have also reduced the time A0-A7 is valid down stream from 74ls374.

At some point as clock speed increases the extra delay breaks the logic.

At 4MHz the minimum hold time from ALE low to AD7-0 tristate is 30ns. The 74LS04 adds 15ns delay maximum (typically 10ns), so it should be OK even at maximum CPU clock speed.
 
Obviously a 373 would be better, but it's not essential.

For something looking for Z80 type then OE needs to set output to tri-state during DMA and RESET. Z80 DMA needs all 16 address lines. Z80 chips like SIO will not work to full function.

Some Z80 based computers had even more restrictions. For example the Mattel Aquarius (which I am currently working with) does not allow interrupts! And yet its 'Quick Disk' drive used a Z80 SIO.

[ali6x944]

An inverter connected to clock input 74ls374 does change the edge.
You have a slow #3


What else happens when you do just this much?
Everything takes time. The inverter delays the change 74ls374 clock signal.
You are now capturing A0-A7 at a later time. Is A0-A7 still valid at this time?
You have also reduced the time A0-A7 is valid down stream from 74ls374.

At some point as clock speed increases the extra delay breaks the logic.

At 4MHz the minimum hold time from ALE low to AD7-0 tristate is 30ns. The 74LS04 adds 15ns delay maximum (typically 10ns), so it should be OK even at maximum CPU clock speed.
 
Obviously a 373 would be better, but it's not essential.

For something looking for Z80 type then OE needs to set output to tri-state during DMA and RESET. Z80 DMA needs all 16 address lines. Z80 chips like SIO will not work to full function.

Some Z80 based computers had even more restrictions. For example the Mattel Aquarius (which I am currently working with) does not allow interrupts! And yet its 'Quick Disk' drive used a Z80 SIO.

For slow speed the 74ls374 with inverter should work.
Replace with a 74ls373 as soon as you can get one.

There are other logic families that you could use in place of LS

You said you have a 74ls273
You could replace grant's logic on his CP/M version that insures that ROM is in memory on cold boot with this chip.
The extra 7 could be used in the future change memory map or other functions.

but wait! this means that I can run this chip if the CPU's clock out/system clock is 4MHz...
system clock in my test setup is 2MHz,  so if I use 74ls04 it will definitely work

[Bruce Abbott]

in my test setup is 2MHz,  so if I use 74ls04 it will definitely work

I don't think the clock frquency makes any difference, but the CPU's rated speed does (4MHz CPU has shorter hold time than 1MHz CPU). In practice bus capacitance will hold the data for a while in tri-state anyway (longer if all chips on the bus are CMOS/NMOS rather than bipolar TTL).   

BTW your NSC800 looks pristine. Where did you get it from?

[C]

but wait! this means that I can run this chip if the CPU's clock out/system clock is 4MHz...
system clock in my test setup is 2MHz,  so if I use 74ls04 it will definitely work

Yes it should work.
Being new you need to look at big picture.

Just because you got one small part to work that does not mean to total system will work!
All timing  must be in bounds for NSC800 to function properly.

This is not a change that could be made to an existing system and be expected to work. It could work fine or it could mess up the timing and make it fail or intermittent.

An existing system could use ALE as a signal that states ADDRESS Valid & Stable. This is no longer true when 74ls374 is used as A0-A7 is not stable or valid.

ALE is an important signal when you read data sheet.
In the data sheet A0-A15 is valid and has been on the bus for a time before ALE. The timing of other signals is based on ALE

Need to remember that the 74ls373 is a follow input then hold the input.

The 74ls374 is put input on output some time after clock edge with a delay from clock edge while changing.

So with the 74ls374, you have high address (a8-A15) address data valid & stable before ALE and low address(A0-A7) becomes valid some time after ALE and down stream circuits must handle this change properly.

All parts that use the separate A0-A7 have less time.

If you look a little closer at how long AD0-AD7 is valid after ALE
th(ADL) is 30ns for 4mhz part, 35ns for 3.5mhz part, 60ns for 3mhz part.
This suggests that internal time delays in the NSC800 logic creates these signals.

Look at and OPCODE read cycle or Memory read using 4mhz part.
Low address is valid at TS(AD) {40ns} before ALE
RD gos low tDAR {160ns} after ALE

So for the 74ls373 low address is stable 200ns before - the time it takes for input to output delay of 74ls373(36-38ns) before RD low.
With 74ls374 and inverter you have 160ns - 10-15 ns for inverter - input to output delay of 74ls374 (32-38ns) before RD low
So low address stable time is now 50-60ns less.

I went in to detail here while this little change is fresh in your mind.
What looks ok in a small part of circuit,  could easily break the system.

The point I am trying to make here is that one small change can have a huge effect on the remaining parts of the system.
You have to get the logic correct.
You also have to get all the time delays accounted for.
Need to keep this in mind when working with logic.



 

[ali6x944]

current update on the project:

also the parts I ordered from Ebay didn't reach Saudi yet, this includes the Z80 and the Eprom programmer....
I also bought some 74HC595, I will use those in the eprom programmer I'm currently working on.
sorry C I was not able to run arduino bootloader on atmega32a, but I will try my best to get it up and running.

[legacy]

yup. Excellent! Sooner or later I will design a GB cart with EagleCAD, allowing people to have an alternative to the hack I presented here. Your EPROM programmer is excellent for this job too since it can program FLASH as well as NVRAM and UV-PROM

For UV-PROM, I got a marvelous UV-tube from recycling equipment from an hospital's division. It was used to make a surgical knife  free from bacteria and/or other living microorganisms, but it's enough OK to be uses as UV-PROM eraser, it just takes more times, something like 25 minutes of exposition instead of 10, but it didn't costed an eye of my head. I just had to build a metal box to put the UV-tube inside 

[ali6x944]

yup. Excellent! Sooner or later I will design a GB cart with EagleCAD, allowing people to have an alternative to the hack I presented here. Your EPROM programmer is excellent for this job too since it can program FLASH as well as NVRAM and UV-PROM

For UV-PROM, I got a marvelous UV-tube from recycling equipment from an hospital's division. It was used to make a surgical knife  free from bacteria and/or other living microorganisms, but it's enough OK to be uses as UV-PROM eraser, it just takes more times, something like 25 minutes of exposition instead of 10, but it didn't costed an eye of my head. I just had to build a metal box to put the UV-tube inside 

Mm.... Interesting...
My younger brother and I are big fans of Nintendo games, he asked me a while ago to modify his GB advanced SP cartridges to be programmable , I saw the cartridge mode u did and I was impressed, I'm really excited to see more...
Good job m8!

[C]

In some of your videos you use a pointer that conducts electricity, Not a great idea!

In your NSC800 video
  You talk about many chips replacing one  373.

Most times it is a bad idea to replace the simple with more complex.

So compare the two, Your many chips vs 373.

With the 373, you have a changing of outputs when ALE goes high. ALE going low holds the now un-changing outputs while letting inputs change with no effect.

How many times does your version upset this smooth change of signals?
Does it have times when output goes unknown?
Does it have glitches in the output?
If you are using CPU clock in the circuit, how does a CPU clock frequency change effect the circuit?
Does it _____

Really break down your design and look at the results of your circuit, Really understand it.
Like using an inverter with 374 most have side effects. Some are not so good, some are bad and it is possible that some are great. With out understanding the circuit, you don't know.

By break it down, you are looking at the logic and the time it takes the chips to operate.

Note that the graphs in the datasheet could give you the wrong idea of actual times evolved. Good idea to actually look at the detail in datasheet.

sorry C I was not able to run arduino bootloader on atmega32a, but I will try my best to get it up and running.

1. Program your current arduino board with ISP program.
2. Connect your  arduino board to atmega32a pins needed to program atmega32a chip.
3. Use link to atmega32a arduino bootloader program for the data to be programmed in to the atmega32a.
4. Now you can use arduino ide to program the atmega32a via the serial port just like your current  arduino board .

Think you know all this, but now you have some numbers to use to get help with problem step.