help! how to make a nsc800 computer?

[ali6x944]

this is the current design before modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4OXg5QnBfeU5lX2s/view?usp=sharing

this is the design after modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4d2ZNazluaVlQb1U/view?usp=sharing

this the design using 74ls541:
https://drive.google.com/file/d/0B5vW-k7HbsL4Ukd1QW4xaWxjb2s/view?usp=sharing

In some of your videos you use a pointer that conducts electricity, Not a great idea!

true, I will change it in the future...

In your NSC800 video
  You talk about many chips replacing one  373.

Most times it is a bad idea to replace the simple with more complex.

So compare the two, Your many chips vs 373.

With the 373, you have a changing of outputs when ALE goes high. ALE going low holds the now un-changing outputs while letting inputs change with no effect.

How many times does your version upset this smooth change of signals?
Does it have times when output goes unknown?
Does it have glitches in the output?
If you are using CPU clock in the circuit, how does a CPU clock frequency change effect the circuit?
Does it _____

I think it will be fine at steady state, but I have my concerns on the transitions, I'm still not sure yet...
at steady state, the circuit will behave as expected and will not create unknown states.

[C]

this is the current design before modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4OXg5QnBfeU5lX2s/view?usp=sharing

this is the design after modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4d2ZNazluaVlQb1U/view?usp=sharing

Both have errors
From what I see in these two circuits, I would think you do not understand how the 374 works.

Re-read the datasheet of the LS374
Then look at NSC800 datasheet
Figures 9a,9b,10a,10b

What is on the 374 outputs? Is it always the low address?
 

One problem has a simple fix in this simple circuit. Connect  LS374 pin 1 to logic low.
This leaves one more problem in above.

this the design using 74ls541:
https://drive.google.com/file/d/0B5vW-k7HbsL4Ukd1QW4xaWxjb2s/view?usp=sharing


I think it will be fine at steady state, but I have my concerns on the transitions, I'm still not sure yet...
at steady state, the circuit will behave as expected and will not create unknown states.

What is the input to output time of the 74LS04?
What is the time  from pin 1 of the 74LS374 to output on?
What is the time  from pin 1 of the 74LS374 to output off?
What is the time  from pin 1 and pin 19 of the 74LS541 to output on?
What is the time  from pin 1 and pin 19 of the 74LS541 to output off?

Now that you have time data, what happens when ALE changes?

Note:  Output off is the High Z state of the output.
          Output on is all output states not High Z

[Bruce Abbott]

I think it will be fine at steady state,

I don't think it will be fine because the maximum allowable clock out period is 6.7us. You can't stop the clock, it has to keep going to preserve the CPU state.

The EN pin on a 374 does not control the clock, it enables the outputs. When EN is high the outputs are turned off and all your LEDs will go dark, but the registers inside the 374 will still be clocked. In the first 2 circuits you should connect the inverted ALE signal to CLK, and EN to ground.  The last circuit with the 541 is good, but probably isn't necessary.

[ali6x944]

this is the current design before modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4OXg5QnBfeU5lX2s/view?usp=sharing

this is the design after modification:
https://drive.google.com/file/d/0B5vW-k7HbsL4d2ZNazluaVlQb1U/view?usp=sharing

Both have errors
From what I see in these two circuits, I would think you do not understand how the 374 works.

Re-read the datasheet of the LS374
Then look at NSC800 datasheet
Figures 9a,9b,10a,10b

What is on the 374 outputs? Is it always the low address?
 

One problem has a simple fix in this simple circuit. Connect  LS374 pin 1 to logic low.
This leaves one more problem in above.

those are the schematics I tried after the original schematic that used inverted ALE to LS374'S CLK or just ALE to LS374's CLK , with both setups /OE to ground.
they don't work properly as u said previously...

the third schematic is the solution to replace the LS373 and it works in 4 steps :
1)when the ALE is Low:
the /OE of the LS374 is low so the output displays whatever is in the register, while G1-G2 of LS541 are high turning the buffers tri-state.

2) when the ALE transitions from low to high:
the /OE of the LS374 is not effected by transitions but by state; as it gets high there will be a Output Disable time of 25ns*, the CLK of is only effected by positive edges,so whatever is in the register isn't changed, while G1-G2 of LS541 are going low after 15ns* of the transition of the ALE due to the propagation delay of the inverter, the LS541 is going to display the outputs after 38ns* of  G1-G2 of LS541 are going low due to output enable time, and it will take 18ns* for the data in A0-A7 to propagate through the gate.


3)when the ALE is High:
the /OE of the LS374 is high turning the register outputs tri-state, while G1-G2 of LS541 are low showing whatever is happening on the A0-A7.

4) when the ALE transitions from high to low:
the /OE of the LS374 is not effected by transitions but by state; as it gets low there will be a Output Disable time of 25ns*, the CLK of is only effected by positive edges,so whatever is in the register changed to what is in the A0-A7, while G1-G2 of LS541 are going high after 15ns* of the transition of the ALE due to the propagation delay of the inverter, the LS541 is going to display the outputs after 38ns* of  G1-G2 of LS541 are going high due to output disable time.
 
*: note that all times are maximum values from the datasheet from tpHL or tpLH, or tpHZ,tpLZ,tpZH,tpZL propagation delays
I have a poor understanding of these timing diagrams, so I really don't know how do they behave so I assume the timing events are sequential.

[C]

Using this
https://drive.google.com/file/d/0B5vW-k7HbsL4Ukd1QW4xaWxjb2s/view

1)when the ALE is Low:
the /OE of the LS374 is low so the output displays whatever is in the register, while G1-G2 of LS541 are high turning the buffers tri-state.

OK

2) when the ALE transitions from low to high:

+25ns LS374 off
+53ns LS541 on (15ns + 38ns)
You have a high Z time of 28ns between the two chips.
This is OK

3)when the ALE is High:

OK

4) when the ALE transitions from high to low:

+15ns LS374 captures current low address
+25ns LS374 ON 
+43ns LS374 Output changes  (15ns+28ns)
+53ns LS541 OFF (15ns + 38ns)
You have both outputs on for 28ns between the two chips
In addition to this you have old low address changing to current address at 43ns.
You will have one or more bits of low address with different levels.
You are guaranteed a logic level fight for 18ns

A second way to look at this is, when ALE falls you have had a valid low address, but then goes unknown for a time and then back valid while chips die or have a shortened lifetime. 

I would list this circuit as a fail.

With just a LS374 with ALE inverted to LS374's clock. you have a valid low address apx 43ns after ALE, Also important fact is that last valid low address is on low address bus before this time.
The LS374 costs 83ns of valid low address time.
With low address valid 43ns after ALE, this also has to be worked around everything that uses low address.
While the LS374 works you have on going problems with everything that needs low address.
A memory chip that latches it's address on CS will need a delayed CS of ALE low + >43ns

Your circuit above does try to correct these problems, but fails with two outputs enabled at same time glitch after ALE low.

Keep in mind that the logic timing of the Z80 & NSC800 both try to keep need for additional logic to a MIN while using common parts of their time like memory chips.

The timing must work for both the NSC800 and what is connected to the NSC800. For a memory chip to function properly the NSC800 timing must be ok for what the memory chip needs or you have to add extra logic.

[Bruce Abbott]

+15ns LS374 captures current low address
+25ns LS374 ON 
+43ns LS374 Output changes  (15ns+28ns)
+53ns LS541 OFF (15ns + 38ns)
You have both outputs on for 28ns between the two chips
In addition to this you have old low address changing to current address at 43ns.
You will have one or more bits of low address with different levels.
You are guaranteed a logic level fight for 18ns

There is an easy fix for this possible bus conflict. Just insert two LS04's in series between CLK and OE, which will delay OE by ~18-20ns relative to CLK. With this modification the 374 registers should already be loaded with the correct data by the time OE activates, so both 374 and 541 outputs should be the same. However there might still still be a short-term conflict when ALE goes high.

To eliminate bus 'fighting' you can add add resistors (eg. 1k) in series with the 541 outputs, which will limit current draw if the 541 and 374 outputs are momentarily different. The Mattel Aquarius uses this technique to read character and color data from two different RAM chips at the same time. The resistors effectively split the bus in two during the video display phase, while still allowing data to flow freely to/from either RAM chip during the CPU phase.
 

The timing must work for both the NSC800 and what is connected to the NSC800. For a memory chip to function properly the NSC800 timing must be ok for what the memory chip needs

This is not a problem if you use fast enough memory. 'Modern' memory chips are much faster than what was available back when the NSC800 was introduced, eg. 70ns vs 250ns.

Older peripheral chips may be a problem, but ali6x944 can cross that bridge when (if) he comes to it. By that time he may been able to source some 373's, but in the mean time why put him off? I say first just try the 374 alone (without the 541) and see what happens!

ali6x944: if you are serious about doing this then you should look at getting an oscilloscope or logic analyzer. It's the only way to see what is actual happening in your circuits. A lowly 5MHz dual trace analog scope should be sufficient.

[ali6x944]

ali6x944: if you are serious about doing this then you should look at getting an oscilloscope or logic analyzer. It's the only way to see what is actual happening in your circuits. A lowly 5MHz dual trace analog scope should be sufficient.

I do have a rigol DS1000Z series scope, but I have big problems with it lately with the second channel vertical ranges, I contacted rigol tech support but no proper reply adressing the issue since I first contacted them in July 5,2017...

[Bruce Abbott]

I do have a rigol DS1000Z series scope, but I have big problems with it lately with the second channel vertical ranges, I contacted rigol tech support but no proper reply adressing the issue since I first contacted them in July 5,2017...

You can get by with 1 channel, but 2 channels are better for doing comparative timing measurements. What exactly is wrong with the second channel?

[C]

SN74LS04
[url]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf] [url]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf[/url]
SN74LS374
http://www.ti.com/lit/ds/symlink/sn54ls373.pdf
SN74LS541
http://www.ti.com/lit/ds/symlink/sn74ls541.pdf

As I have stated many times for low address latch,
#1 74ls373 is best choice
#2 74ls374 with inverted clock will work with some costs down stream on low address. The costs here are less valid low address time & loss of when low address is valid. Adding parts it is possible to create a new low address valid, but you might not need to based on what is connected.

#3 The circuit with 74LS374 & 74LS541
 state 2 The high Z time must be >0
State 4 is a mess
More chips might cure problem, but then you have poor design and more chips.
Here you are trying to switch outputs with zero time delay & with out putting old low address on bus again.
The best you could get is the two active outputs with same logic level.
A high Z state time could work but is not a good design.

Think about Bruce's two inverter fix.
From 74LS04 data sheet
max delay is 15ns so two inverters in series is 30ns
But typical is 9ns high & 10ns low for a total of 19ns
This is at load listed in data sheet. Less load could be faster.
Which time also effects the time I listed in last post.
So using typical timing changes times in my list, some places it gets better while others gets worse.
As stated above, the best outcome is still a bad design. 
The resistors on 541 output is also a hack that can cause problems.
Best choice is to call this a bad design and pick #1 or #2 from above

For Good design you need to know when things are valid & not valid..
For a Z80, MREQ tells you two things, It's a memory access and supplies a time reference to when address became valid.
For NSC800 a lot of timing is based on fall of ALE. Time Reference to when address became valid is one of these.

So to stop messing around you need to know what chips you are going to try to use, what memory chips, what IO.
Then you need to look at the timing these chips need to function.

For a memory or IO read with the AD0-AD7 bus  you have the NSC800 driving lines then the memory or IO driving and back to NSC800 driving. You need a high Z time between each change of drive.
For a memory chip this is OE.
For CPU this is normally RD.
Check the timing from the two data sheets.
Here the two High Z times must be >0ns
Note that there is a difference if the memory read is an OP code read or Data read.
You could have four High Z times.

Each timing requirement must be valid.
The RD signal, more times need to be verified.
You now have one pin done on memory chip, repeat for all pins.

Doing this detail work is much quicker then trying to find poor design problems with test equipment.

[C]

ali6x944,
Look at your copy of the NSC800 data sheet.

Page 1
  you should see
"Low-Power CMOS Microprocessor"

You need to look at page 3 to see what this means
VIH   Logical 1 Input Voltage  min 0.8 VCC
VIL   Logical 0 Input Voltage   max 0.2 VCC

When you compute this max 0.2 VCC= 1V and 0.8 VCC= 4V with VCC = 5V
This is CMOS input logic levels.

Lower you see
VOH1 Logical 1 Output Voltage IOUT = -1.0 mA           2.4 V
VOH2 Logical 1 Output Voltage IOUT = -10 uA             VCC -0.5 V
VOL1 Logical 0 Output Voltage IOUT =   2 mA              0.4 V
VOL2 Logical 0 Output Voltage IOUT = 10 uA               0.1 V

You have standard output TTL logic levels for xxx1
and CMOS output for low current pin loads xxx2.

If you look at the SN74HC04
http://www.ti.com/lit/ds/symlink/sn74hc04.pdf
You see that the outputs of the SN74HC04 can meet the required input levels of NSC800

If you look at the SN74LS04
http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf
You see that the outputs of the SN74LS04 WILL NOT meet the required input levels of NSC800

An LS or TTL logic output  can not be an input to NSC800

An NSC800 output can be an input to LS or TTL logic.
For HC Logic, There is a problem with NSC800 Logical 1 Output Voltage,
IOUT needs to be some value <-1.0 ma to be > HC High-level input voltage

There is a third logic family HCT which is TTL input levels & CMOS Output levels.

One memory chip I see in your list is MB8464A
This is a TTL input & Output level memory chip.
Read data (ttl level output) from this chip will not meet NSC800 input levels.
The fix is to put a 74HCT245 between the NSC800 & MB8464A and logic to control 74HCT245.


Note the NSC800 output currents above are very low.
Driving LED's directly with NSC800 can be a fail.
best to use an inverter or buffer to drive LED's

Details like this from data sheets in this post need to be correct to have working system.

[Bruce Abbott]

Good point on the CMOS input levels. The vast majority of CMOS CPUs are TTL compatible, but the NSC800 is not. It always pays to read the datasheet carefully. For example the Z80 is TTL on all inputs except the clock, which is 0.45V low and Vcc -0.6V high.

74LS04 high output is ~4.25V unloaded, but above 3.5V the low to high transition will be slow due to the low source current. This can be fixed by adding a pullup resistor. However it would be better to use CMOS logic. I threw away most of my LS TTL chips many years ago, and now only use HCT logic (or HC if TTL compatibility is not required). 

The MB8464A shouldn't be a problem. Though the specs say 2.4V minimum, the data outputs are actually CMOS. I tested an MB8464A with 1k pull downs on the data lines and the high level was 4.5V.

 
 

[ali6x944]

The vast majority of CMOS CPUs are TTL compatible, but the NSC800 is not...

well, that bad I guess.... and its pretty weird...
see I got the NSC800 from an old board, I didn't remember it containing any CMOS compatible or CMOS chips, the fact is all were LS TTL with two or so LM339 comp-op amps and real time clock chip.
its a long time since I saw it so I might be wrong....
https://drive.google.com/file/d/0B5vW-k7HbsL4OXJ0TmpmeFMzT1U/view?usp=sharing

[C]

It's just a detail that has to be correct.

Z80 Clock needs large voltage swings and has lower current drives on output.

A Micro processor tries to make things easy and use less logic on a board.
But in doing so you have to verify that timing works and all logic levels are met.

You should trust the data sheet until you can prove it wrong.
For example, MB8464A data sheet says TTL logic levels, Bruce says "It's OK SEE CMOS level " but that does not mean your MB8464A is CMOS logic, need to test yours if you want to use as CMOS Levels..

[Bruce Abbott]

I got the NSC800 from an old board, I didn't remember it containing any CMOS compatible or CMOS chips, the fact is all were LS TTL

TTL compatibility was achieved by using pull-up resistors.   

Bruce says "It's OK SEE CMOS level " but that does not mean your MB8464A is CMOS logic, need to test yours if you want to use as CMOS Levels..

Never hurts to test. However the vast majority of CMOS memory chips do output full 0-5V logic levels, even if the datasheets don't admit it.

[ali6x944]

TTL compatibility was achieved by using pull-up resistors

That's great, but how dose pull-ups effect the VIL and VIH of the processor?
Also I will try to get 74LS373 in the near future...
Thanks a lot for the help m8s

[Bruce Abbott]

I suggest you try to get 74HC or 74HCT parts. The advantage of HCT is that it is compatible with both CMOS and TTL logic levels. CMOS parts also have lower power consumption, which may become important when you add more ICs.

[C]

To get high speed out of first Z80's even resistors were not good enought for Clock input. The 74HC or 74HCT parts made it easy to drive Z80 clock input.
Need to remember that old circuits were built with parts on hand or could be purchased at that time. All parts have gotten better over time. First ram chip was 1k bytes and used a lot of power. A 2k byte replaced it in some places. If you design using old parts you will probably see higher costs , more chips and less function.

A 373 does not cost much, but you could save time and money with an order of more parts.

Would suggest you try to draw up what you want connected to the NSC800. Check out as much as you can like logic levels and timing. Then let some of us here look at design, Could save you a lot of time.

Keep in mind that I think getting a Z80 running will be faster, and with this step complete the NSC800 could be easer.

 

[ali6x944]

I received the TL866CS programmer this morning, I tested it and it was working nicely
I started to read the roms and saw a couple of interesting things...
the NSC800N I have probably came from some automotive engine tester, I presume from the roms...

[ali6x944]

I tested many others and they contain code I guess...

[ali6x944]

The question repeats its self, how dose the pull-ups effect the VIH and VIL of the nsc800n?
Also I got an LS373 finally and I guess we can move on finally to the computer memory since I have the Minipro programmer up and running...

[SeanB]

Z80 is only really able to drive 2 LSTTL inputs on the output lines, so a buffer is mandatory on all output lines to get reliable operation at high speeds. If you run without buffers the output is not going to always be able to discharge the line capacitance fast enough going from 1 to 0, so the data latched ( always latched at the clock transition, though the time before is required for non clocked logic to ripple through to the correct state) will eventually be wrong. Buffers must be driven from a fast buffer, driven by the Z80 to select direction for the data bus.

This is because the Z80 was originally made in Nmos and this has TTL compatability, but it is not as high current capable as a bipolar TTL device, and thus the on state resistance of the switches in the IC will be less able to discharge or charge the capacitance of longer data buses. At least the Z80 clock is able to be driven from TTL levels, the original 8080 required a much stricter clock drive, with much steeper edges and much higher currents into the clock, and often had the clock running off a 12V rail and diode clamps to provide the fast edges and high level voltage.

[Bruce Abbott]

Z80 is only really able to drive 2 LSTTL inputs on the output lines, so a buffer is mandatory on all output lines to get reliable operation at high speeds...

This is because the Z80 was originally made in Nmos and this has TTL compatability, but it is not as high current capable as a bipolar TTL device, and thus the on state resistance of the switches in the IC will be less able to discharge or charge the capacitance of longer data buses.

True, but this may not apply to a small system which doesn't operate at 'high' speeds or have 'longer' buses.

One famous example - the Sinclair ZX81- had a Z80 clocked at 3.25MHz driving two 1K RAM chips, ROM, keyboard matrix (!), and bipolar ULA (uncommitted logic array) without any bus buffers. I built a backplane for it which had 4 slots for extra RAM and I/O devices - no buffers! And it all worked perfectly.

[SeanB]

Zilog only guaranteed that it would drive 2 LSTTL loads, but a typical chip would drive more at room temperature. Problems arose with long bus lines, extremes of clock speed and running near the extremes of supply voltage range and temperature. Run at 4V5 and at 0C and most would work, but a few would give occasional glitches. Zilog wanted it to work from -55C to 125C and from 4V5 to 5V5 with absolutely no glitches at all.

[ali6x944]

so would I need buffers between the LS373 and NSC800?
and the question repeats its self, how dose the pull-ups effect the VIH and VIL of the nsc800n?

[SeanB]

LS373 and the LS240 are the bus buffers, used to buffer the most common data, address and control buses out of the chip so they can drive much higher loads. Direction on the bus buffer has to be connected to enable the right flow of data, and as you likely will have some slight probability of bus contention there normally is a series resistor of 33R in each of the 8 data bus pins that serves both as current limiting and damping. Generally works without them, but a lot of designs do use them.