help! how to make a nsc800 computer?

[ali6x944]

I saw these in the web yesterday, the 8085 is incredibly similar to the NSC800 form an interfacing prospective, I think they could be adapted to the NSC800...
https://drive.google.com/file/d/0B5vW-k7HbsL4dE9kdkFEM1VNR2c/view?usp=drivesdk
https://drive.google.com/file/d/0B5vW-k7HbsL4NzB2Tjh2Uk1kc0k/view?usp=drivesdk

[Bruce Abbott]

The NSC800 was designed to replicate the bus interface of the 8085, but with Z80 registers and instruction set. It also has the Z80's DRAM refresh and interrupt modes.

Provided you are not using dynamic RAM or peripherals that use Interrupt Mode 2, the 8085 should be BUS compatible. Only problem is the pinouts are completely different, so it won't be a 'drop in' replacement.   

[ali6x944]

This is great news
But what is interrupt mode 2? Is there way to fix the problem?
Also don't worry about the cpu's RAM its all SRAM.

[Bruce Abbott]

But what is interrupt mode 2? Is there way to fix the problem?

Either don't use peripherals that need IM2, or stick with the NSC800.

Also don't worry about the cpu's RAM its all SRAM.

This is not so much of a problem now as it was when the NSC800 was developed. Back then static RAM was very expensive. I was paying $24 each for HM6116's, which would be over $300 for 32k. Still, even at that price it was worth it for the simpler circuit and battery backup capability.

The advances in memory density are staggering. In the early '80s I scavenged a 64k RAM expansion from an 8 bit IBM mainframe. It used 2102 1kx1 static RAMs and was the size of a small suitcase. Many desktop computers used 2116 16kx1 DRAMs, which needed +12V and -5V (and tended to blow up if the power was sequenced wrong). Then some Japanese companies developed a 64kx1 +5V only DRAM, and everyone went mad. Over 64 thousand transistors in a single chip!
       

[ali6x944]

It is really interesting to know about the development of RAMs over the years but why did the older cpus like the intel 8080 and older ram used so many supply voltages?
Also I am currently checking the wiring of the first schematic  , I have wired both the AS6C62256 32k SRAM and the SST39SF010 1M-bit flash eeprom...

[ali6x944]

I finished testing, and the result is weird...
the S0 and S1,/RD,/WR,/M indicator LEDs were all active which means its in Acknowledge of Interrupt state, note that its not a power-up quirk and I have checked all interrupt pins and they were pulled high as should be , also when I click on reset button the /RD and /WR are disabled which indicate that it is working...
I will try to use the working channels on my scope to test if  its really working in Acknowledge of Interrupt state because its really hard to tell if the LEDs are flashing
note that the eeprom is new thus all positions are 0xFF in the eeprom and suspect this is the responsible...

[Bruce Abbott]

why did the older cpus like the intel 8080 and older ram used so many supply voltages?

The higher voltage was needed to power the transistors used in them. Some very early digital chips used depletion mode PMOSFETs that ran on 12~17V (eg. National Semiconductor's SC/MP).  Early dynamic RAMs also needed a negative bias voltage. Later DRAMs generated the negative bias voltage internally.

The Intel 8080 and Texas Instruments TMS9900 (used in the Ti99/4A) are probably the only popular CPUs that needed multiple power supplies. Other lines such as the 2650, Z80, 6800 and 6500 were always +5V only. The RCA CDP1802 could take up to 10V, but was normally run on 5V.

note that the eeprom is new thus all positions are 0xFF in the eeprom and suspect this is the responsible...

0xFF is RST 38, the external interrupt vector. With the ROM filled with this value it will continuously jump to 0x0038 while (attempting to) push the PC onto the stack.

BTW I just received these from eBay seller hifi-szjxic. Genuine original 'unretouched' and well used ICs! (described honestly as such in their listings). I am now designing a PCB for the NSC800.
 

[ali6x944]

Cool
Now both of us will have the same reference point, but what will you use your NSC800 for?
I suspect some graphics related application, from the RGB to NTSC/PAL Encoder...
I hope you best of luck in your project

[ali6x944]

I have flashed the ROM to all 0x00 but the LEDs are still on...

[Bruce Abbott]

I have flashed the ROM to all 0x00 but the LEDs are still on...

Can you upload a photo of your current setup? A schematic too if you can draw one.

For single-stepping the CPU you may able to use the /PS pin. Here's what the datasheet says about it:-

9.4 POWER-SAVE FEATURE
The NSC800 provides a unique power-save mode by the
means of the PS pin. PS input is sampled at the last t state
of the last M cycle of an instruction. After recognizing an
active (low) level on PS, The NSC800 stops its internal
clocks, thereby reducing its power dissipation to one half of
operating power, yet maintaining all register values and in-
ternal control status. The NSC800 keeps its oscillator run-
ning, and makes the CLK signal available to the system.
When in power-save the ALE strobe will be stopped high
and the address lines [AD(0–7), A(8–15)] will indicate the
next machine address. When PS returns high, the opcode
fetch (or M1 cycle) of the CPU begins in a normal manner.
 

[ali6x944]

https://drive.google.com/file/d/0B5vW-k7HbsL4YlNjZ3F1aEJtdXM/view?usp=drivesdk
This is the setup, and for the schematic I used the first configuration, the one without the mux.
I must say it is a pretty smart trick, but using the /ps control at 4MHz clock is pretty difficult in the sense that how can I step single instructions if some has different numbers t states and M cycles ?

[Ian.M]

I must say it is a pretty smart trick, but using the /ps control at 4MHz clock is pretty difficult in the sense that how can I step single instructions if some has different numbers t states and M cycles ?

That would be fairly simple - like two 74xx series chips and two switches.  First you need to decode the Opcode Fetch state. See the first row of the table on page 9 of the datasheet.  A 74xx138 3 to 8 line decoder could do the job, generating a low going /M1 pulse during Opcode Fetch.  Connect that /M1 pulse to the /CLR pin of 1/2 74xx74 dual D type flipflop, with its Q output connected to NCS800 PS pin.  Connect a Step/Run switch and a pullup to the flipflop's /PRE input to force Q high for Run mode. Use the other half of the flipflop as a debouncer - pullups and a SPDT pushbutton grounding /PRE when pressed and /CLR when released, unused inputs tied low - output from Q to CLK of first half to clock in a '1' from the first half  D pin which needs to be tied high. 

Result:  It runs with the toggle switch at Run, and single steps on a button push when its at Step.   You could also hook up the output of a 555 timer to effectively press the step button (use the Discharge pin and wire it to /PRE) to apply a slowish variable auto-step pulse to let you 'slow run' it.

It does however have a flaw - Z80 instructions that take a prefix (i.e. the modifiers to operate on IX and IY  rather than HL) and bit instructions etc. have two M1 cycles, so you have to press the button an extra time for every prefix.  Decoding the prefixes to detect multi-M1 instructions is more trouble than its worth without a GAL or FPGA.

You've got plenty of space on your breadboards and should be able to hook it up in half an hour or so.

[ali6x944]

I must say it is a pretty smart trick, but using the /ps control at 4MHz clock is pretty difficult in the sense that how can I step single instructions if some has different numbers t states and M cycles ?

That would be fairly simple - like two 74xx series chips and two switches.  First you need to decode the Opcode Fetch state. See the first row of the table on page 9 of the datasheet.  A 74xx138 3 to 8 line decoder could do the job, generating a low going /M1 pulse during Opcode Fetch.  Connect that /M1 pulse to the /CLR pin of 1/2 74xx74 dual D type flipflop, with its Q output connected to NCS800 PS pin.  Connect a Step/Run switch and a pullup to the flipflop's /PRE input to force Q high for Run mode. Use the other half of the flipflop as a debouncer - pullups and a SPDT pushbutton grounding /PRE when pressed and /CLR when released, unused inputs tied low - output from Q to CLK of first half to clock in a '1' from the first half  D pin which needs to be tied high. 

Result:  It runs with the toggle switch at Run, and single steps on a button push when its at Step.   You could also hook up the output of a 555 timer to effectively press the step button (use the Discharge pin and wire it to /PRE) to apply a slowish variable auto-step pulse to let you 'slow run' it.

It does however have a flaw - Z80 instructions that take a prefix (i.e. the modifiers to operate on IX and IY  rather than HL) and bit instructions etc. have two M1 cycles, so you have to press the button an extra time for every prefix.  Decoding the prefixes to detect multi-M1 instructions is more trouble than its worth without a GAL or FPGA.

You've got plenty of space on your breadboards and should be able to hook it up in half an hour or so.

Sorry , but I didn't understand your circuit layout and theory of operation...

[Ian.M]

I've drawn it out from the above description.

• When SW1 is closed, it forces U2B:Q and /PS high allowing the NSC800 to run normally.
  .
• When SW1 is open, /M1 from the state decoder clears U2B, taking /PS low during instruction fetch and stopping the NSC800 at the end of the instruction cycle.  Pressing SW2 clocks a single '1' into U2B, releasing /PS till the next M1 cycle.  U2A is wired as a SR flipflop and debounces SW2.
  .
• The optional 555 circuit is a simple slow squarewave oscillator, with a switched potentiometer so it can be turned off.  When on, it is equivalent to repeatedly pressing the step button.  Holding down the step button would pause the autostep feature.

H.T.H.

[ali6x944]

Thanks a lot Ian
I will build it now and inform you with the result.

[ali6x944]

Hi everybody,
it has been a while now, sorry for the late reply...
I was having problems with my scope as you know and I needed to send it to China.
It is fixed now, and again sorry for the late reply.
the circuit is not working properly the /PS line does not change at all, no matter what I do the /PS line stays at 5v...
I checked the connections and they seem alright, the 555 timer oscillates as expected, everything seems ok...
quick question thou, is Y7/6/5/4/2/1/0 connected to anything?

[Ian.M]

No, the other /Yn pins aren't connected to anything - you might need them later for peripheral interfacing.

Are you getting low going /M1 pulses for each instruction?   
Is U2A debouncing the stepPB button and producing a clean high going output on  its Q pin, and are you seeing a repeating high going pulse at its Q pin when the 555 is enabled?

[ali6x944]

 It is working now
It was the bloody NE555 when I replaced it with the cmos TLC555CP it worked nicely
Thanks a lot Ian 

[ali6x944]

I will use the following addressing technique:
https://drive.google.com/file/d/0B5vW-k7HbsL4dE9kdkFEM1VNR2c/view?usp=drivesdk
Again I have reflashed the rom to 0x00 but I will not connect the ram just yet to see if it will work or not...

[ali6x944]

https://drive.google.com/file/d/1xskY6pgiYRTDF3C9KDveT1otbeTKdtm-/view?usp=drivesdk
Here it is, the circuit seems to work ....
Y0 on the memory decoding 74ls138 is switching that's good...
But the data bus displays a binary 00111000, which seems to be a conditional jump to program location with respect to program counter and the displacement d, based on limited testable flag status. Most specifically opcode 38 or "JR C,d2"
I guess.

[Bruce Abbott]

Which output of the LS138 is active? What is the memory address, and what data were you expecting?

[ali6x944]

Only Y0 and Y1 are going low and high forming some sort of switching action...
I have flashed the rom to 0x00 so I would be expecting nops.

[ali6x944]

To be more exact, the address bus should be incrementing  while the data bus should show nops.

[ali6x944]

but the address bus only increments if the clock the 4 MHz clock is not interrupted by the /PS line going low...
basically when SW1 is pushed the circuit seems to run correctly...
but what I don't understand is why the data bus doesn't show nops?