Are you trying to read/write to/from embedded block ram (EBR) inside the device? or an SRAM chip connected externally?
I am using the Lattice XP2 Brevia2 dev kit:
http://www.latticesemi.com/latticexp2-breviaI was under the impression that the SRAM ports defined on the board (data0..7 = 1,2,5,6,7,8,9,10, address0..16 = 119, 120, 121, 122, 123, 124, 125, 127, 129, 130, 131, 132, 133, 134, 137, 138, 141, chip select = 142, output enable = 143, and write enable = 144) was the same as the EBR, but that it was a real SRAM chip.
Internal SRAM blocks tend will have their specific 'ports' for which I'm sure there are verilog examples. (they will be the obvious, address, data, read enable, write enable, chip select etc..). External SRAM is only slightly trickier. Both would most likely require a state machine.
I believe that's what I'm trying to use, but I can't figure out how to "multiplex" the data pins. I presume I need an inout, but how does that work? I will assign at some point when I'm writing, and otherwise use 8'bZ or 8'bX so it's not connected when not writing?
I'll admit, for something seen as 'basic' by many, I too had trouble finding verilog examples for SRAM. I ended up having to start completely from scratch, which forced me to think about it, and helped me learn. If you are still struggling, and its for external SRAM, I'll post a verilog snippet I made years ago. It won't have the functionality you want, as in incrementing and decrementing address based on buttons, its just a module for hooked up external SRAM to internal busses.
It would be great to see the example. I believe I understand everything in concept, but I am having difficulty translating thought into the mechanics of Verilog syntax.
UPDATE: I have just found this link which demonstrates the use of an inout. It has a flag indicating when data is put onto the wire, and when not use N'bZ for the value:
inout example on altera.comThank you,
Rick C. Hodgin