Help:Lattice diamond, ERROR - Cannot place PIO comp "DCK" on PIO site "A9/PT22C"

[joy586210]

Dears,
I'm trying to set pin 'A9/PT22C' of Machxo3l as one of MIPI DSI clock output pins. But below message is reported:
ERROR - Cannot place PIO comp "DCK" on PIO site "A9/PT22C" (I/O bank 0).
ERROR - Cannot place PIO comp "DCK" on the proposed PIO site "PT22C / A9" because the types of their IOLOGICs are incompatible:
the associated IOLOGIC comp "DCK_MGIOL" has been set to "ODDR4" mode (of type "TIOLOGIC"), while the IOLOGIC site is of type "TSIOLOGIC".
ERROR - Please check the pin locking in your preference file.


It's very simple to re-produce this error, just download RD1184 reference implementation from url http://www.latticesemi.com/view_document?document_id=51308 and set device as 'LCMXO3L-6900C-6BG256C', click 'translate design' in process tab, then open tools->Spreadsheet View, set DCK to pin A9. Then if you click 'place and route design', above error message will appear.

May I know how to avoid such error message, or I have to redesign my 4 layer pcb to use another pair of pins for DCK?

 Your help is greatly appreciated.

[Kilrah]

Don't know this part and the doc can't be downloaded without login, but it looks like an I/O type conflict.
While FPGAs have configurable I/O levels/types it is typically only settable in the scope of an entire I/O bank/site/whatever it's called by the manufacturer, i.e. all pins in the same bank need to use the same type. Moving that signal where you did (different part than in the reference design?) makes it conflict with other things that this bank is already used for.

You need to check whether either that signal or the others in the bank can be safely set to match the other, if not then yes you need to move it somewhere else and potentially redesign for it.

[joy586210]

Yes, when I move it to another pin in the same bank, it will be OK.
Or I can use A9 as input of clock, but I can't use it as LVDS25E output.

Thus I have to get a new pcb board 

[uncle_bob]

Hi

Welcome to the learning experience of "place all the pins and do a check before you layout the PC board". People laugh at me for doing that. I learned why you do it the hard way, just like you.

Bob

[joy586210]

I have read manual many times before prepare schematic, but there is still issue left....

Now I need to find a way to map ODDR output internally to pin A9.
Any good advice?

[mikeselectricstuff]

Hi

Welcome to the learning experience of "place all the pins and do a check before you layout the PC board". People laugh at me for doing that. I learned why you do it the hard way, just like you.

Bob

+1 - there are so many potential gotchas that it's  really a good idea to compile at least a minimum bare-bones design with all inputs and outputs as per the PCB to check for any constraints you'd not noticed in the thousands of pages of datasheets.   

[uncle_bob]

I have read manual many times before prepare schematic, but there is still issue left....

Now I need to find a way to map ODDR output internally to pin A9.
Any good advice?

Hi

The basic problem is that the pins are similar in many respects, but not identical in every respect. It is easy to get into the "anything can go anywhere" excitement. In fact, there are generally bank voltage restrictions on logic types, dedicated clock inputs and outputs and pin sets designed for specific use (serial / de-serial, RAM, configuration ...).

If you are using a leaded part, do what everybody else does. Unsolder the pin and put a really small piece of wire on it. Run the wire over to where it needs to go. I ....errr ... have seen ... a lot of boards like that.

Bob

[joy586210]

Thanks, I will fly a wire for that...

Just find in RD1184:
The HS data signals (D0, D1, D2, D3) for the RX and TX D-PHY IP's should only use A/B IO pairs

So may be the same restriciton for DCK.