FIFO refers to first-in-first-out scheme, but IMHO it is confusing here because you do not read everything you acquire, but only the window. So, it's better to stick with the term (circular) buffer.
You have already answered your question. Say, you determined that your trigger point is stored at address X. Then you start reading from buffer[X-pre_trigger] to buffer[X+post_trigger], which is (1+pre_trigger+post_trigger) = (window_size) times. It'll wrap around automatically, just make sure your buffer has power of 2 size, such as 1024. You also need to make sure that your buffer size is at least (pre_trigger+1+trigger_detection_latency), otherwise ADC will overwrite the buffer before you read it.
I don't understand why you need a second FIFO unless you want to switch between clock domains. You can process the data immediately as you read it. While you're doing this, ADC continues to acquire, so your buffer needs dual access - writes by ADC and reads at desired addresses.