Hi Chaps,
Apologies for the wall of text, but I tried to get as much info into the OP as possible.
I'm designing a board that needs a high speed link between two units, the link needs to be 16 bits wide, and fully async, as each bit is driven from a discreet component.
The current design uses a direct link from a STM32 to a TLK2541 serdes, and yes, I designed this with only cursory looks at the datasheet.
BackgroundAs such, I have a free running 100Mhz clock driving both the REF_CLK as well as the TX_CLK of the TLK2541, the idea was that the TLK would manage all the serdes and encoding duties, leaving me with a 16 bit bus to do with as I please. The use case for the 16bit bus is 4 bits connected to high speed 485 drivers, and 12 bits connected to the micro to implement a 4 lane 8 bit bus with two control bits for Data Ready and ACK.
D[0:7] - uC connected Data
D[8:9] - Lane Select (Purely a software function)
D[10] - Data Ready
D[11] - ACK
D[12:15] - Direct connect to 485 transceiver
These connections are duplicated on the RX side of each board for BiDi comms
Since I can get away with a fair bit of jitter on the micro side, I devised a DR/ACK system that would control the bus at any jitter level, and allow me to not care about the "sample frequency" of the serdes at 100Mhz. With this in mind, I am sure I can get good transfer at up to 10Mhz. (The serdes would "sample" the 16bit bus at 100MHz)
ProblemSo I built it, and started playing, only to realize that I really was stupid in not studying the datasheet. The TLK2541 needs sync words to be sent on the data lines every now and then to keep the PLL locked and to align the bytes on the TX/RX lanes. This of course needs to happen in sync with the TX_CLK. So no way I can get that working as the TX_CLK is free running, and I dont have control of all 16 bits.
Solution IdeaAnd this is where I need your opinions/help.
The idea I have is to use the TLK2501 serdes, this device is capable of automatically generating both the sync words, as well as idle patterns to keep the link active. As an upside, it also has RX_LOSS to tell you the link is down, something the TLK2541 lacks. The auto-generation still needs to be triggered in sync with the TX_CLK though, but instead of being placed on the bus, all it needs is a pin to be toggled.
So I was thinking of using a small CPLD like the CoolRunnerII in-between the serdes and the rest of the circuit, to "manage" the link. The CPLD will be fed the free running 100Mhz clock, and it is in charge of supplying the clock to the serdes. The idea here is that I halve the bandwidth of the parallel side of the link, and allow the CPLD to generate a sync word for every 2nd clock pulse, but only accept/reveal the valid data on its pins on every other clock pulse, thus hiding the sync from the rest of the circuit, and allowing me to do as I please with the 16bit bus, albeit now at 50Mhz sampling, not 100Mhz.
So the questions:
Will the above small function fit in a CPLD? (Xilinx XC2C24)
Will the CPLD be fine at 100Mhz?
The cost difference between a CPLD and a FPGA is small, is it worth doing this in an FPGA and have some future proofing in there?
I'm a bit of a CPLD/FPGA noob, having only done two small projects with them, so please help a brother out. If anything is not clear, ask away.
Thanks,
JVR