TI has MCUs with Ferroelectric RAM!

[rs20]

Maybe I'm late on this news, but this seems intriguing:

http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/msp/ultra-low_power/msp430frxx_fram/what_is_fram.page?DCMP=FRAM&HQS=fram

You we think they're overhyping this a little, or is it pretty genuinely revolutionary for some applications? I particularly like these aspects:
-- Upload firmware updates directly into FRAM at line speed, no need to do the buffer/high-voltage-flash-erase/rinse/repeat dance with flash
-- Upload state into FRAM continuously/on power loss to allow settings to remain non volatile, where normal flash would wear out too fast/be too slow/consume too much power.
-- Eliminate external EEPROM chips entirely

Did I just make a fool of myself? 

[oPossum]

You are 4 years late. They are on the third generation of MSP430 FRAM parts now.

There are several Launchpad FRAM dev boards available for a reasonable price.

[rs20]

Thanks, I suspected as much  -- but my question still stands, which could be better stated as "Is flash/eeprom really that unsuitable for many tasks? Does FRAM really lead to longer-lasting/more featureful end user products?"

[oPossum]

It is useful for a few very specific applications. It is very low power and has very high write endurance. If you need that, then it may be a good choice.

[Fsck]

they even have a "for dummies" book on using fram.

for most electronics, probably no useful increase in lifetime as most things tend to be outdated and replaced before they fail.

[nctnico]

I have used FRAM in a couple of my designs. Mostly because of the high (sometimes infinite) write endurance. But you have to be aware that a read is 'destructive' so it has to rewrite the data. In other words: a read cycle is also a write cycle.

[mikeselectricstuff]

I have used FRAM in a couple of my designs. Mostly because of the high (sometimes infinite) write endurance. But you have to be aware that a read is 'destructive' so it has to rewrite the data. In other words: a read cycle is also a write cycle.

I'd be a little concerned about the effect of power glitches if reading program code from FRAM...

[6thimage]

I have used FRAM in a couple of my designs. Mostly because of the high (sometimes infinite) write endurance. But you have to be aware that a read is 'destructive' so it has to rewrite the data. In other words: a read cycle is also a write cycle.

I'd be a little concerned about the effect of power glitches if reading program code from FRAM...

I remember reading, when they first came out, that they essentially have a large enough capacitor in them so that they can always write the data back after the destructive read.

[poorchava]

I have used FRAM in a couple of my designs. Mostly because of the high (sometimes infinite) write endurance. But you have to be aware that a read is 'destructive' so it has to rewrite the data. In other words: a read cycle is also a write cycle.

I'd be a little concerned about the effect of power glitches if reading program code from FRAM...

But on the other hand every eeprom and flash emmory has an internal write cycle too, and in case it gets disrupted and you don't detect and handle the situation accordingly you might bee in some trouble too.

[mikeselectricstuff]

I have used FRAM in a couple of my designs. Mostly because of the high (sometimes infinite) write endurance. But you have to be aware that a read is 'destructive' so it has to rewrite the data. In other words: a read cycle is also a write cycle.

I'd be a little concerned about the effect of power glitches if reading program code from FRAM...

But on the other hand every eeprom and flash emmory has an internal write cycle too, and in case it gets disrupted and you don't detect and handle the situation accordingly you might bee in some trouble too.

There's a big difference between possible glitches on read vs. write when every read of program memory carries some risk.

[rs20]

But on the other hand every eeprom and flash emmory has an internal write cycle too, and in case it gets disrupted and you don't detect and handle the situation accordingly you might bee in some trouble too.

There's a big difference between possible glitches on read vs. write when every read of program memory carries some risk.

Though I think the claim is that the FRAM chips have an internal cap that makes it impossible to corrupt the data due to a power-cut-on-read. Whereas the flash write cycle disruption issue is not at all theoretical.

[wraper]

FRAM is highly radiation resistant. Therefore you won't be able to erase them with X-rays like flash memory.

[6thimage]

FRAM is highly radiation resistant. Therefore you won't be able to erase them with X-rays like flash memory.

The FRAM memory itself is completely radiation resistant (ionising radiation doesn't affect magnets), but the control circuitry isn't, which is the weak point. So powered off FRAM can be blasted with whatever radiation you like, but if it's running then you'll get problems at a certain dose level - still much better than flash though.

[oPossum]

FRAM is highly radiation resistant. Therefore you won't be able to erase them with X-rays like flash memory.

(ionising radiation doesn't affect magnets)

FRAM is ferroelectric, not ferromagnetic.

http://en.wikipedia.org/wiki/Ferroelectricity
http://en.wikipedia.org/wiki/Ferromagnetism

[helius]

X-rays are comparatively low in energy, generally below 1 MeV. The really energetic particles that can disrupt memories come from radioactive decay or cosmic rays. So-called "rad hardened" chips used for spacecraft need to withstand "single event upsets" (SEUs) from multi-MeV particles. ECC memory helps a lot.

addendum: I searched for more info on this topic and it looks like very low energy X-rays are actually the ones most responsible for leaking charge off the floating gate, in what I presume to be a similar process to UV erasing an EPROM. At these low energies disruption to active circuits (sense amps etc) is unlikely.
(http://www.spansion.com/support/application%20notes/x-ray_inspection_on_flash_an.pdf)

[6thimage]

FRAM is highly radiation resistant. Therefore you won't be able to erase them with X-rays like flash memory.

(ionising radiation doesn't affect magnets)

FRAM is ferroelectric, not ferromagnetic.

http://en.wikipedia.org/wiki/Ferroelectricity
http://en.wikipedia.org/wiki/Ferromagnetism

Not sure why I started going on about magnets, obviously I wasn't thinking straight. But the point still stands, the FRAM storage is not susceptible to radiation (as charge polarisation is not affected), only the control circuitry is.

X-rays are comparatively low in energy, generally below 1 MeV. The really energetic particles that can disrupt memories come from radioactive decay or cosmic rays. So-called "rad hardened" chips used for spacecraft need to withstand "single event upsets" (SEUs) from multi-MeV particles. ECC memory helps a lot.

ECC does help quite a bit, but it does have its limits. From what I've seen, rad-hardened electronics tend to come in two flavours, those with larger features (so the ionisation is a lower percentage) and redundancy (i.e. ECC, triple redundancy and voting logic).

addendum: I searched for more info on this topic and it looks like very low energy X-rays are actually the ones most responsible for leaking charge off the floating gate, in what I presume to be a similar process to UV erasing an EPROM. At these low energies disruption to active circuits (sense amps etc) is unlikely.
(http://www.spansion.com/support/application%20notes/x-ray_inspection_on_flash_an.pdf)

I know that the south Atlantic anomaly causes a lot of hassle for satellites (with cubesats, containing non-rad-hardened components, being reset or having corrupted memories when passing through it). But the Van Allen belts are quite high energy (1 - 100 MeV). But as you say, low energy radiation (i.e. UV and x-rays - remembering that UV and soft-x-rays cross over) can cause a lot of problems, but it is very dependant on the environment you are in and what you are using (I think analogue electronics will just have higher noise).

The way that UV EPROM is erased is exactly the same effect (have a look at the photo-electric effect on wikipedia). UV will erase flash memory as well, but you have to de-cap it first. Some microcontrollers have metal guards over there write-once fuses to stop someone from de-capping them and then reading the data off.

On a bit of a side note, a lot of servers are now starting to see effects from background radiation. With the increase in memory density, and the decrease in feature size, the amount of charge on each floating gate in a RAM module is smaller, requiring less radiation to flip each bit, making them more susceptible.

On an even more of a side note, but still kind of related (and will hopefully make up for my magnet screw-up earlier), the feature size of flash memory could be reduced further than it already is, but with the reduction in size comes an increased tunnelling effect, which reduces the data life of the memory. The thousands of years normally quoted is in part due to background radiation exposure, but a large proportion of it is the probability of the charge tunnelling off the floating gate. It is in part why memory manufactures are looking at ways to stack memory on top of each other inside a chip (which has just reminded me of Hitachi's get perpendicular video).