How do they pump 500Msps with an ordinary FPGA (spartan 6) into a DAC

[ali_asadzadeh]

Hi,
The Siglent SDG5000 Function Generator Teardown  was quiet fascinating. but I wanted to know how do they do it with a low Cost FPGA assuming that Siglent  may have used a spartan 6 device because of the price point! so what's the trick? when you synthesis a normal counter inside the FPGA it would not go much more than 100MHz!

Code: [Select]

reg [15:0] cnt;
always @(posedge clk) cnt <= cnt+1;
Any Ideas?

[Lukas]

By doing things in parallel. An FPGA may not be fast enough to generate 500M 8bit samples a second, but it can do 100M 5x8bit samples. The DAC in the SDG5000 has a 16bit parallel LVDS interface, the only thing running at 500MHz/1GHz are the transmitters in the FPGA. They've got built-in serializers that take a wide data stream from the FPGA fabric.

[codeboy2k]

... and don't forget it will be pipelined.  I would say that's the key here.

Those 5 x 8 bit counters operating at 100 Mhz are not merely operating in parallel, they are going to be pipelined so they each generate one 8 bit sample staggered at 1/5th phase shifts (with respect to each other)

The rough timing diagram below should make it clear.
Each rising edge of a cnt entity gives one 8-bit output at a rate of 100 MHz . Taken together you get 8-bit samples at 500 MHz.

 ( timing done online at http://wavedrom.com/editor.html )

Code: [Select]

{
 signal: [
  {name: 'cnt1',   wave: '01.........0.........1....|',node:'.a...................f'},
  {name: 'cnt2',   wave: '0....1.........0.........1|',node:'.....b'},
  {name: 'cnt3',   wave: '0........1.........0......|',node:'.........c'},
  {name: 'cnt4',   wave: '1..0.........1.........0..|',node:'.............d'},
  {name: 'cnt5',   wave: '1......0.........1........|',node:'.................e'},
  {name: 'clk500', wave: '0.1.0.1.0.1.0.1.0.1.0.1.0.1',node:'..u...v...w...x...y...z'}
],
 edge: [ 'a~u', 'b~v', 'c~w', 'd~x', 'e~y', 'f~z']
}


[slateraptor]

 ( timing done online at http://wavedrom.com/editor.html )

Nice tool.

[codeboy2k]

I really like it, since you can play around interactively with the 0's 1's and dots to get the timing aligned right

Every change to the source text is rendered immediately in real time on the diagram.   There's a menu at the bottom right (hard to spot sometimes) which offers a user guide and save options.   There's a tutorial on the home page.

I posted the link since I think it's helpful to others to share the tool I used

[nctnico]

Hi,
The Siglent SDG5000 Function Generator Teardown  was quiet fascinating. but I wanted to know how do they do it with a low Cost FPGA assuming that Siglent  may have used a spartan 6 device because of the price point! so what's the trick? when you synthesis a normal counter inside the FPGA it would not go much more than 100MHz!

Code: [Select]

reg [15:0] cnt;
always @(posedge clk) cnt <= cnt+1;
Any Ideas?

You can get much higher count frequencies in a Spartan6. IMHO 250MHz should be achievable when the place&route parameters are tweaked correctly (trial & error) and then you can use wider data paths and DDR output flipflops.

[krenzo]

http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

Look at page 18.  Using ODDR2 or IDDR2 registers, you can maintain 500 Mb/s input/output rate with any speed grade Spartan 6.

http://www.xilinx.com/support/documentation/user_guides/ug381.pdf page 61 explains the ODDR2 primitive.

[Howardlong]

 ( timing done online at http://wavedrom.com/editor.html )

Nice tool.

Indeed, looks like it's worth spending a little time getting to grips with that.

[marshallh]

With a simple 16bi counter you could easily hit Fmax (usually 400mhz or something useless).
With a 32bit counter you may only get 300mhz, 64bit.. 200mhz, etc.

I wrote a 5Gbps USB3 IP core that processed all data in a 125mhz clock domain, 4 symbols per cycle (36 bits). Used DDR i/o regs to bring that out to the 250mhz, 16bit PHY.

[ali_asadzadeh]

Thanks guys, but do low end spartan 6 devices like XC6SLX9 have any serializer ?I do not think so, what happens when you wanted to increase the sample rate higher, for example 1GSPs, also the SRAMS that are located near the FPGA are 200MHz devices...too

Does a low end spartan have enough DDR registers for two SRAMS and two 16Bit DAC?

[hamster_nz]

Thanks guys, but do low end spartan 6 devices like XC6SLX9 have any serializer ?I do not think so, what happens when you wanted to increase the sample rate higher, for example 1GSPs, also the SRAMS that are located near the FPGA are 200MHz devices...too

Does a low end spartan have enough DDR registers for two SRAMS and two 16Bit DAC?

Yes, most pins have a ISERDES2 / OSERDES2, rated to about 1Gb/s depending on speed grade.

See table 25 of http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

Also, each pin has DDR registers.

[JoeN]

Stoopid question.  If you had that FPGA (fairly inexpensive) and that DAC (fairly inexpensive), how hard would it be to roll a cheap signal generator yourself?  Is the output of the DAC basically converted from I to V and then that is it, maybe run it through a high speed op-amp to allow for amplitude setting?   Do the free FPGA tools allow you to create all the "parts" necessary to do this like the LVDS serializers?  Is it possible to get it onto a 2 layer board (assuming a QFP FPGA part rather than the BGA parts)?  Does anyone do this sort of thing or is this just too time consuming to design and write all the HDL (and presumably C for a microcontroller somewhere in the mix) for?

[hamster_nz]

Stoopid question.  If you had that FPGA (fairly inexpensive) and that DAC (fairly inexpensive), how hard would it be to roll a cheap signal generator yourself?  Is the output of the DAC basically converted from I to V and then that is it, maybe run it through a high speed op-amp to allow for amplitude setting?   Do the free FPGA tools allow you to create all the "parts" necessary to do this like the LVDS serializers?  Is it possible to get it onto a 2 layer board (assuming a QFP FPGA part rather than the BGA parts)?  Does anyone do this sort of thing or is this just too time consuming to design and write all the HDL (and presumably C for a microcontroller somewhere in the mix) for?

It is like building a house using only a swiss army knife - you could do it if you really had to.... But it most probably better to use the correct tools

[JoeN]

It is like building a house using only a swiss army knife - you could do it if you really had to.... But it most probably better to use the correct tools

Well, what are the correct tools?  It seems to me we know the correct parts because Siglent succeeded with them.  I am not sure what the correct tools are.  It seems to me even with the correct tools and the correct parts it's a big hill to climb.  What I wonder is if all you want to do is create get sine/square/ramp/triangle waves with various amplitudes what would it take to do that with these parts?  Does the free version of ISE support LVDS at this speed, will a 2 layer board crap on these signals, how hard is designing all the analog glue?  That last part is the part I bet is the hardest of all.  I can see something like this working great till you get to 5Mhz (or choose a speed) and then the signal just becoming crap from a poorly designed board.

[nctnico]

ISE will support the high speeds. No problem with that. You'll need at least a 4 layer board. The best route is probably to get a base board which has the Spartan6 mounted on it and create an add-on board with the DAC + analog circuitry. The add-on connector should have a lot of ground pins for signal integrity.

[hamster_nz]

As examples, if you get some good resistors you can build R/2R analog DACs, but only to about 6 bits precision before things get ugly, and to about 150 M Samples per sec.  You will likely need a video amp to buffer the signal too. With that part count you might as well use a seperate DAC chip and get better performance.

Likewise a 1-bit audio range DAC is trivial to implement in an FPGA - all that is needed is a pin and a low pass filter, then an opamp to buffer it - but a  I2S DAC will give superior performance at about the same part count.

You can do these things, just not as well as dedicated silicon can.

The board layout can be a problem, but only really when traces start to act as transmission lines - I've pushed about 500Mb/s over differential pairs  through 0.1" headers, on a two layer board.  It really shouldn't have worked but it did....

[JoeN]

I was talking about using at least the two main parts that Siglent choose, the Spartan 6 and the AD9783 DAC (or similar like TI DAC3482), that's why I was talking about LVDS.  Did not mention trying to roll my own resistor network DAC.  But now at least I understand your earlier cryptic comments about building a house with a swiss army knife.  That is not what I am suggesting.