How do you sequence power rails?

[technix]

This is about the AT91SAM9260 project I am designing. For the sake of simplicity I am using 4 power rails for the chip:
* VDDBU: 1.8V backup voltage, sourced from an LP2985-1.8 LDO from the backup battery.
* VDDCORE: 1.8V rail for core voltage and PLL (VDDCORE and VDDPLL on the chip,) sourced from a LM3671-1.8 switch mode regulator.
* VDDIO: 3.3V rail for digital I/O and memory (VDDIO[01M] on the chip,) sourced from an LM3671-3.3 switch mode regulator.
* VDDANA: 3.3V rail for analog converters, sourced from an LP2985-3.3 LDO.

In the AT91SAM9260 datasheet, there is a specific power sequencing requirement when a backup battery is used: the VDDIO must not be powered before VDDCORE rises above 1.5V, but must rise above VIH within 166us and above VOH within 518us. How do you sequence this? Can I just use the EN inputs of the regulators? Or should I use a few MOSFETs switching the power rails after the regulators have been up, using the system controller MCU for this?

[NorthGuy]

If your regulators have PG(power good) pins, you just can connect them to the EN pin of the next generator. You need to make sure the voltage levels are Ok.

[nctnico]

Usually there is a companion power supply chip from the manufacturer or a third party which is tailored to provide the right power supply sequencing. This is the easiest method.

[BrianHG]

For one of my projects, I used a cheap 50cent PIC as a timer to sequence a bunch of supply rails on my FPGA/DDR2/HDMI-ADC board which had to use 2 different types of cycles depending on if the unit was previously powered on and off, but, the 5v from a HDMI video source stayed on.  The manufacturer's data sheet have a bunch of 74HC logic for the HDMI chip + the Altera FPGA had a different custom chip.  I said F- it all, put in the PIC and had it not only handle the power enables for the regulators, but, the reset lines & flash boot-prom nConfig reset for the FPGA as well.