How to add time delay in verilog code

[gauravmp]

Hi,

I'm wondering how you could add delay in verilog code for an FPGA. I understand, I can add a for loop and have it go for a number of cycles, but is there a better way. I'm more so looking for delays to a few seconds.

Can I have another clock go at a frequency very slow so that I could do this. If so, how could I implement it?

I'm using Altera MAX 10 FPGA and Quartus II 15.0

Thanks

[John_ITIC]

No, there's no better way. A digital, synchronous design uses counters to create delay. You can simply count up an integer or reg and act when reached whatever delay you need.

[mikeselectricstuff]

You must always keep in mind that you're describing hardware, not writing a program.
So you need to think how you would implement a delay in hardware - make a counter  (or maybe a shift-register - that can sometimes be more efficient for small counts), decide how many bits it needs, how to clock it, reset it and detect when it gets to the value you want.

[helius]

Of course, there's nothing preventing you from using a software approach in a FPGA. You simply need to build a machine in HDL that interprets the code you want to write. Or select an existing soft core that matches the needed capabilities.

[obiwanjacobi]

Output it to external pins and use external hardware to delay the signal?
This might be feasible if the time is long and you want to save FPGA resources...?
[2c]

[gauravmp]

Thanks guys! was able to do it!