How to design a proper memory map for an 8-bit microprocessor that would keep everything simple and neat?
An "ideal" z80-like system has 64k of RAM in the memory address space and a separate IO space.
1) do I need to make ROM at the beginning of the memory space?
Execution begins at 0 after reset, but various things (notably CP/M) want RAM at low memory locations. General purpose microcomputers (ie that ran CP/M) would use some sort of logic to "temporarily" change the address decoding logic at reset, so that ROM could be (normally) in high memory. (The very start of the ROM would "jp REALROMLOC" and then reset the address decode logic. Or copy itself to RAM, jump to the copied code, and reset the address decode logic.)
2) does interrupts need to be addressed to the ROM memory space?
Z80 has several interrupt modes. One allows an interrupt controller to place arbitrary instructions on the bus, a 2nd uses a vector table that can be anywhere in memory, and the 3rd jumps to 0x38.
3) which is better in organising memory, pages or arbitrary assigning of memory space?
Traditionally, you decode the upper address bits to figure out which "bank" of memory to use. I guess that's "pages." It made lots of sense when a "bank" of memory was 1k to 32k. Now that RAM chips are likely to be 64k or more, you might end up doing something more like decoding "holes" in the address space to insert other types of memory.
4) if I use a GDC like the NEC uPD7220AD or intel 82720, do I need to include the memory for the GDC as addressable memory for the NSC800 even though the processor can't address it directly -or at least this is what I think-?
I don't know anything about GDCs.
5)for peripherals in the minimalistic computers made by Grant Searle he uses the z80's /IORQ and /MREQ to choose the the things he whats to address and he treats them as two separate 64k banks - see:http://searle.hostei.com/grant/z80/SimpleZ80.html - is it possible to do the same with a dual function pin on the NSC800 or similarly in the intel 8085?
The NSC800 is supposed to be Z80 compatible, but the 8085 (and 8080) only has 256 bytes in the IORQ address space.
"memory mapped IO" was a thing for a while (and required in CPUs like 6800, 6502, etc, that didn't have separate IO address spaces), but got traded off with the desire for more memory. 8080 code will still only address 256 IO locations.
6) if I have certain programmable I/O in my computer, say a UART chip or a PIA or keyboard interface chip or even the GDC it self, do I need a special address for the chip or can I use RAM? if I have to use a special address for the chip how to choose it properly?
You have to decode the IO address space finely enough to fit all your peripherals in the 256 bytes, and coarsely enough to fit all the addresses that the IO chip uses. 8080-era peripherals tend to use "few" addresses compared to modern peripherals.
7)if an I/O chip has its own separate memory does I need to treat it as a totally independent system, thus designing its own memory map?
It depends on the IO chip.
8)which is the best option regarding addressing, using chips or glue logic?
It depends on the size of the system. If you're NOT doing a general purpose computer, decoding the upper address bits into banks and putting one device in each bank was pretty popular. For a 32k RAM/32k ROM system, that usually means just putting A15 into the CS of one chip, and into CS/ of the other (most RAM/PROM chips have both positive and negative logic chip selects.) Using the 74138 on the upper three bits (as other have suggested) gives you 8 8k banks. GALs or other programmable logic let you do more complex decoding (put in the upper 8 bits, get out sepate chip selects for 56k of RAM, 4k of ROM, and 8 memory-mapped peripherals of 512bytes each, plus the logic to do the special reset-mapping (on a 22v10)
1) what comes first in ROM, front end setup or back end setup? I/O setup or OS setup?
Doesn't really matter. Review CP/M's "BIOS" concept, where the OS expects certain services from the ROM (or other user-provided SW)
2)is it possible to create a C ROM?
3)is it possible to create a mix language ROM?
Maybe. Depends on your C compiler.