Author Topic: How to Port This VHDL to Verilog?  (Read 1613 times)

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Offline Sal AmmoniacTopic starter

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How to Port This VHDL to Verilog?
« on: July 11, 2016, 03:17:11 am »
Verilog gurus: I'm just learning Verilog (Systemverilog actually) and don't know how to map the following VHDL to Systemverilog:

Code: [Select]
   process(CLK, Next_State, RESET)
   begin
       if (RESET = '1') then Present_State <= ST0;
       elsif (rising_edge(CLK)) then Present_State <= Next_State;
       end if;
   end process;

If I use the following always construct, I don't know how to mix posedge and non-posedge in the sensitivity list-- the synthesizer flags it as an error:

Code: [Select]
   always_ff @(posedge CLK, posedge RESET, Next_State)

I want the always block to run whenever Next_State changes, but I also want it to be synchronous with the positive edge of CLK.
Complexity is the number-one enemy of high-quality code.
 

Offline ataradov

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Re: How to Port This VHDL to Verilog?
« Reply #1 on: July 11, 2016, 04:01:05 am »
Just remove Next_State and RESET from the sensitivity list.
Alex
 

Offline Sal AmmoniacTopic starter

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Re: How to Port This VHDL to Verilog?
« Reply #2 on: July 11, 2016, 04:06:26 am »
Just remove Next_State and RESET from the sensitivity list.

I need to handle asynchronous resets too, so I need that in the list. If I remove Next_State from the sensitivity list and just assign it to Present_State on every rising clock edge that would work, even if Next_State hasn't changed.

Thanks.
Complexity is the number-one enemy of high-quality code.
 

Offline ataradov

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Re: How to Port This VHDL to Verilog?
« Reply #3 on: July 11, 2016, 04:10:34 am »
If I remove Next_State from the sensitivity list and just assign it to Present_State on every rising clock edge that would work, even if Next_State hasn't changed.
Well, yes, but it is the same thing. If Next_State has not changed from a previous assignment, then reassigning it to Present_State again will have no visible effects.

I'm pretty sure that's what original VHDL is doing.
Alex
 

Offline kfnight

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Re: How to Port This VHDL to Verilog?
« Reply #4 on: July 11, 2016, 03:14:20 pm »
You want something like this.

Code: [Select]
// Active-high asynchronous reset.
always_ff @(posedge CLK, posedge RESET)
begin
    if (reset == 1'b1)
    begin
        Present_State <= ST0;
    end
    else
    begin
        Present_State <= Next_State;
    end
end
 


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