Verilog gurus: I'm just learning Verilog (Systemverilog actually) and don't know how to map the following VHDL to Systemverilog:
process(CLK, Next_State, RESET)
begin
if (RESET = '1') then Present_State <= ST0;
elsif (rising_edge(CLK)) then Present_State <= Next_State;
end if;
end process;
If I use the following always construct, I don't know how to mix posedge and non-posedge in the sensitivity list-- the synthesizer flags it as an error:
always_ff @(posedge CLK, posedge RESET, Next_State)
I want the always block to run whenever Next_State changes, but I also want it to be synchronous with the positive edge of CLK.