Hi all, I have a challenge that I have not been able to solve. Hopefully someone has seen and solved this before.
I have a system with multiple AVR MCUs on a few different PCBs. All of them communicate with TWI (i2c). One of the PCBs could be intentionally shut down as part of a safety response. The problem is when that AVR is shutdown, the i2c bus (SDA and SCL) is pulled low by the internal IO pin diodes.
I am trying to figure out a simple circuit with FETs that will block the i2c signals from entering the AVR when powered down. I added two N-Fets to the SDA/SCL pins oriented with the SOURCE to the AVR and the DRAIN on the i2c side of the FET. The GATE is driven HIGH by a 10v Zener circuit connected to the main power bus 17v.
The goal is that the when the 17v bus is on, the AVR powers up and the FETs bi-directionally pass the i2c data. If the 17v goes off, the FET's turn off and block the SDA/SCL from being grounded by the AVR. The question I have, is whether the SOURCE of the FET being tied to the AVR pin will be sufficiently grounded to where it will turn on with the gate being charged to 10v will actually create a Vgs of around 10v minus the diode drop.
ADD:
This is an I2C slave only. 5v.
R29 discharges the GATE when 17v is OFF
C13 is just a bypass cap.
Z1 is a simple limiter since 17v is close to the limits of the FETs and could go over.