I'm going to try FPGA for the first time - question

[alank2]

I think MultiSIM is the simulator.  I don't know how to get the logic diagrams in Quartus but see if Tools -> RTL Viewer works.  Or try Google...  I am fairly certain that the feature exists.

I agree that MultiSIM is the simualtor - I saw that mentioned a few times, just don't know how to get it to load.

The Tools -> RTL Viewer WORKS though - thank you!

[spudboy488]

It's Modelsim - https://www.altera.com/products/design-software/model---simulation/modelsim-altera-software.html

[rstofer]

I think MultiSIM is the simulator.  I don't know how to get the logic diagrams in Quartus but see if Tools -> RTL Viewer works.  Or try Google...  I am fairly certain that the feature exists.

I agree that MultiSIM is the simualtor - I saw that mentioned a few times, just don't know how to get it to load.

The Tools -> RTL Viewer WORKS though - thank you!

In the past, the simulator wasn't included in the free software.  That's why I have never used one - I didn't have it!  With Vivado, I do.  But I still haven't come to grips with using it.

ETA:  If you get one of those books that starts out with simple logic circuits and works up, it is very helpful to look at the schematic.  Just so you know what is actually being created...

[Kilrah]

ETA:  If you get one of those books that starts out with simple logic circuits and works up, it is very helpful to look at the schematic.  Just so you know what is actually being created...

One of the good things to know is that a caveat of HDLs is that it's easy to create unwanted latches - so the first thing to look for in the schematic is that you don't see any flip-flops in places where you don't explicitly want some!

[alank2]

In the past, the simulator wasn't included in the free software.

Maybe that is why I can't run it - I am using the free web edition...

[rstofer]

In the past, the simulator wasn't included in the free software.

Maybe that is why I can't run it - I am using the free web edition...

Google around about it.  It wasn't included with the free Xilinx WebPack ISE.  Happily (maybe) it is included with the free version of Vivado.

[alank2]

I'm feeling pretty good tonight about accomplishing something!  I was able to get Grant's awesome CP/M example up and running on the board I ordered and finally today after getting an SD (not SDHC!) memory card, I got it working, formatted with his tool, and running CP/M great.

Just to see if I could - I got out my Saleae and starting tracing what the VHDL for the SD card controller was doing and began to try to tweak it for SDHC operation.  This page was invaluable as was looking at his initialization code in C:

http://elm-chan.org/docs/mmc/mmc_e.html

Once I implemented the CMD8 and modified the result part of the VHDL to process the extra 4 bytes it returned, I got the initialization sequence to work.  After that it was just changing the addressing from byte to LBA and the SDHC now also works!

My next plan will be to attempt to make a single VHDL that detects which type SD/SDHC and deals with each appropriately...

Thanks for all the good information and help in this thread!

[Someone]

In the past, the simulator wasn't included in the free software.

Maybe that is why I can't run it - I am using the free web edition...

Google around about it.  It wasn't included with the free Xilinx WebPack ISE.  Happily (maybe) it is included with the free version of Vivado.

Xilinx ISE has included a simulator for a long time, they switched from a bundled modelsim package to their iSim clone around 2010?? Its not great but it works and the price is right (free).

[rstofer]

I'm feeling pretty good tonight about accomplishing something!  I was able to get Grant's awesome CP/M example up and running on the board I ordered and finally today after getting an SD (not SDHC!) memory card, I got it working, formatted with his tool, and running CP/M great.

Just to see if I could - I got out my Saleae and starting tracing what the VHDL for the SD card controller was doing and began to try to tweak it for SDHC operation.  This page was invaluable as was looking at his initialization code in C:

http://elm-chan.org/docs/mmc/mmc_e.html

Once I implemented the CMD8 and modified the result part of the VHDL to process the extra 4 bytes it returned, I got the initialization sequence to work.  After that it was just changing the addressing from byte to LBA and the SDHC now also works!

My next plan will be to attempt to make a single VHDL that detects which type SD/SDHC and deals with each appropriately...

Thanks for all the good information and help in this thread!

How about a link for the Grant project?  I'd like to see what it entails.

About 12 years ago, I used the Opencores T80 core (Z80) to implement CP/M.  I used a compact flash device to implement the full complement of maximum sized disks.  I actually started out to use the T80 to implement PacMan but got sidetracked.  Later on, I got PacMan running on another board but, alas, we don't have room for a table style video game.  Maybe now that we have moved to a bigger place...

I also implemented an IBM 1130 computer, still using the compact flash device because it has a simple parallel interface (and it's fast!).  I have had it running for several years now.

[Kilrah]

First post of this topic...

[Buriedcode]

As an alternative to modelsim in quartus (there's a free version, but can be a pain to set up) you can use quartus simulator for waveforms that allows relatively straight forward stimulus of inputs - clock, high, low, arbitrary value for buses etc..

Just create a new 'University program VWF' file, add the nodes you want to see and any inputs can be edited for states, transitions, clocks, then 'simulation -> run functional simulation'.  Be sure to change the setting in simulation >options to 'Quartus II simulator'.  I've been using that and its pretty quick and handy for fairly basic tasks.  For qsys stuff I tend to use signaltap II to probe the bus and signals to/from peripherals.  It's the only way I could get acustom master to read from the SDRAM controller - by looking at how the NIOS II did it.

[bingo600]

Just to see if I could - I got out my Saleae and starting tracing what the VHDL for the SD card controller was doing and began to try to tweak it for SDHC operation.  This page was invaluable as was looking at his initialization code in C:

http://elm-chan.org/docs/mmc/mmc_e.html

Once I implemented the CMD8 and modified the result part of the VHDL to process the extra 4 bytes it returned, I got the initialization sequence to work.  After that it was just changing the addressing from byte to LBA and the SDHC now also works!

Alan could you upload a "diff file" for the SDHC part ?

/Bingo

[alank2]

Bingo, I'm working on a removable system right now for it.  I can PM you the SDHC fixed disk version, or if you want to wait a couple of days, I'll have a 4 drive version where you can mount a virtual diskette in any drive.  The virtual diskette can be up to your size in the SD card - for example - my 4GB card has 470 virtual 8MB diskettes.  I've created a mount utility to manage mounting diskettes and it even has a way to mount by name using a file with number,name mappings:

I'm hoping to try my hand at modifying where the OS loads to and can move it up making another 3K of program space next.

Code: [Select]

A>mount
Diskette Mount Tool 1.00.
 
Drive A: contains diskette 0 (SYSTEM).
Drive B: contains diskette 1 (PASCAL).
Drive C: contains diskette 2 (BDS_C).
Drive D: contains diskette 3.

So you could use:

MOUNT B: PASCAL
or
MOUNT C: WORDSTAR
or
MOUNT D: 200

Thanks,

Alan

[mubes]

Back to the OPs' original Q; All this FPGA getting started talk whetted my appetite, so with three weeks vacation coming up I've finally taken the plunge...some thirty years after playing with GALs in University and thinking they were pretty cool.  A poke around eBay led me to this, which is in the UK;

http://www.ebay.co.uk/itm/Altera-Cyclone-IV-FPGA-Learning-Board-EP4CE6E22C8N-and-USB-Blaster-Programmer-/121897534832

...there are cheaper sources for it in China, but it'll come quicker from up the road.  Any comments on it? Be nice, I already clicked Buy Now. I realise the uncommitted I/O is limited, but 8 bit VGA, some LEDs, switches, a buzzer and some other bits will be well above my competence level for quite some time I should think.

DAVE

[Buriedcode]

That board should have everything you need to get started.  Hopefully it'll come with a disk with example projects on it, and pin assignment files so you won't have to manually assign the pins for the memory.  I actually have that board in my watch list.

The only downsides I see are the lack of external IO - thats not much of a problem except when you start to have lots of interfaces, and the medium gate count.  The EP4CE6 is the smallest device in the cyclone IV family, with ~6700 LE's, 270kbits of embedded memory (thats actually more than enough for most applications).   If you're planning on using alteras microcontroller design, it will eat into the LE's quite a bit, but should still leave enough for custom applications - 6000 LE's is a LOT of logic, especially if you use the embedded dedicated memory blocks for large shift registers and FIFO's, then each LE will be used for actual logic.

https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyiv-51001.pdf

I'm not sure I would use the VGA port, but a VGA controller is an excellent starter project (still working on mine!).   All in all its rather basic, but *far* better than a bare board with just regulators and a programmer - some buttons and LED's even just a few are always handy for test outputs and just seeing 'whats happening' - something you really need to learn more complex HDL.

[bingo600]

Bingo, I'm working on a removable system right now for it.  I can PM you the SDHC fixed disk version, or if you want to wait a couple of days, I'll have a 4 drive version where you can mount a virtual diskette in any drive. 

Alan i'll just wait  (thanx)   

/Bingo

[mubes]

@Buriedcode; there is a disk that comes with it, and I found some schematics at;

https://svn.mavipet.sk/svn/fpga_tests/HW/ZRtech/

...the PCB layouts seem to match what I can see in the pics.  Only thing I wish it had is a SD card interface, so I guess that's where some of that uncommitted I/O will be going.   The VGA port was indeed my idea for a starter project...we'll see how that goes!

Regards

DAVE

[mac.6]

A while ago someone posted a video of Nvidia's labs. They indeed had a hardware emulator, which apparently consisted of... a room full of racks full of high-density FPGAs, with a PCIe card sticking out at the end that is plugged into the test PC

I didn't saw the GPU hardware labs while I was at Nvidia, but I worked on Tegra 4i fpga, it was a very big PCB with 8 (up to 10) big virtex (5 and 6 mixed) on it. It was running quite fast compared to Cadence dedicated simulators. The only drawback with this kind of fpga is that they are not always 100% timing accurate.

[alank2]

What do files with .cmp and/or .qip accomplish?

I can compile the VHDL without them and I don't get any errors.

example cmp:

Code: [Select]

component CGABoldRom
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock : IN STD_LOGIC  := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

example qip:

Code: [Select]

set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "CGABoldRom.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "CGABoldRom.cmp"]