Hi eev149, thank you for your reply I really appreciate it.
* Are you sending the 16 bit SPI data out to the device MSB first?
"To upload the sequencer registers, a dedicated serial to parallel interface (SPI) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The address must be uploaded first (MSB first), then the data (also MSB first)."
Yes this is what I have done and verified on the scope. Each bit matches to what I designed. Most of the time to see correlation in my settings and the sensors behaviour.
* Did you check the SPI clock polarity / clock phase / timing to ensure that you're sending proper SPI data?
Yes, as above.
* Are you sending the SPI registers configurations while the IC is held in reset (at least to initialize them)? It is required?
I'm not, I don't think the sensor should be in reset. "... on the rising edge of signal REG_CLOCK and become effective immediately." I assume this means the device would not be in reset.
* Did you check that the power supplies and BIASING / DECOUPLING pins are all appropriately connected so there is bias / power applied as needed whether through certain value resistors or not and that proper decoupling capacitors exist where specified? VHIGH_ADC, VLOW_ADC and all the rest?
Yes, I have been through all of them, schematic, layout and the populated PCB, checked all resistor values, voltage and continuity.
* Did you check the ANALOG OUTPUTS to see if the analog values look as expected given the settings? It should be used to sanity check the resultant ADC values. You should be able to get a nice row of luminance data on a DSO similar to the way you could see a line of NTSC video, etc. Maybe some things would be easier if you set it to generate only one analog output ? I don't know if you need to use both ADCs and both analog outputs for your application. It looks to me like the two analog outputs have to externally be connected to drive the two ADCs since that appears to me to be where the signal actually comes into the ADCs. Did you verify that the analog output values are as expected and that they are connected to the ADCs?
Yes I have been observing the analogue outputs. When I have the OUT1/2 signal connected to the ADC_IN1/2 the voltage would be maximum (no integration) but I could get the signal to lower into the ADC's range by setting the DAC_RAW (DC offset) reg to 0.
* Try setting BLACK bit in SEQUENCER and see if the output tracks the configured DAC_DARK voltage?
That's a good idea I'll try that this afternoon.
* Can't you use the ADC register's BITINVERT bit to see if you can cause the output pixels values to invert or not on command? That may tell you something.
I have done this, BITINVERT does work.
* Why is SEQUENCER:INT_TIME set to that value? Does it have to be <= NROF_LINES in the given mode?
I have tried everything from 0 to 4095, doesn't seem to have any effect.
* IMAGE_CORE TEST MODE two bits allow either the odd or even columns to be forced to Vdd level. This can produce a possibility of every or every other column's pixels being set to the maximum value so it should be considered to generate test output to see if it makes sense when in the test mode.
I have them set to 00 for normal operation.
* DAC_RAW_REG should be checked at different values
Have tried throughout the entire range (0-255).
* DAC_FINE_REG should be checked at different values
Have tried throughout the entire range (0-255).
* DAC_DARK_REG Try at 10000000 or ...?
Have tried throughout the entire range (0-255).
* Note on Power On Behavior At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0).
Serial to Parallel Interface (SPI) To upload the sequencer registers, a dedicated serial to parallel interface (SPI) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The address must be uploaded first (MSB first), then the data (also MSB first).
The elementary unit cell is shown in Figure 9. Sixteen of these cells are connected in series, having a common SPI_CLK form the entire uploadable parameter block. Dout of one cell is connected to SPI_DATA of the next cell (maximum speed is 20 MHz). The uploaded settings on the address/data bus are loaded into the correct register of the sensor on the rising edge of signal REG_CLOCK and become effective immediately.
On power-on, all the internal register of the IBIS4-6600 are reset to 0. All the sensor registers must to be loaded before the sensor is brought out of reset.
I have the sensor in reset for 1s at power on before anything is loaded. I have also tried asserting the REG_CLK before clocking anything in via SPI to clear the shift register but made no difference. Where did you read the sensor settings need applying before bring out of reset?
Many thanks again, I appreciate the effort going through the datasheet and understanding the function of a device like this.
From last night having the OUT1/2 and the ADC_IN1/2 signals unconnected I was getting a varying output that correlated to the amount of light the sensor was exposed to. I did however still got strange results. ADC gain and integration time made no difference to the exposure. The contrast was ridiculously high, obtaining grey on the output was challenging. The DAC reg settings didn't make any difference on the digital output. A calibration procedure is outlined in the datasheet to set the black point offset, you need to keep the sensor in the dark for this, no matter what I set the DAC_RAW register I could not get any output other than zeros output. I did not get time to observe the analogue output at this point, will try that later on.