ICE40, help with PLL in VHDL

[aturcitu]

Hello,

I am having a bad time trying to instantiate PLLs in my ICE40devBoad. It is the first time I am doing this and all the documentation and the Wizard included in IceCube2 is in Verilog.
Since my project is in VHDL I am trying to figure out how would this be in VHDL.

Basically I need to generate a 25MHZ clock fro ma 12 MHZ one. In verilog this would be achieved by this code

  SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
                  .PLLOUT_SELECT("GENCLK"),
                  .DIVR(4'b0001),
                  .DIVF(7'b1000010),
                  .DIVQ(3'b100),
                  .FILTER_RANGE(3'b001),
                 ) uut (
                         .REFERENCECLK(pclk),
                         .PLLOUTCORE(clk),
                         .LOCK(D5),
                         .RESETB(1'b1),
                         .BYPASS(1'b0)
);

Could anyone help me getting this working in VHDL.

Thank you in advance

[pix3l]

Are you using Lattice Diamond? If so, you can use the IPexpress to generate the VHDL files

[ale500]

The ICE parts are supported in Diamond, that's why he is using IceCube2.

Does ICECube2 support mixed language projects ? if so, you can use the verilog module directly.

What you are missing is the generic map (just a guess, I'm a verilog guy).

Code: [Select]


GENERIC MAP (
    FEEDBACK_PATH => "SIMPLE",
    PLLOUT_SELECT =>"GENCLK",
    DIVR => "0001",
    DIVF => "1000010",
    DIVQ => "100",
    FILTER_RANGE => "001"
                 )