Author Topic: ATMEL's CUPL language for their CPLD range of chips, what do you think.  (Read 15408 times)

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Offline Bassman59

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #25 on: October 07, 2015, 10:49:01 pm »
That's what I thought.  They seem to have about 0.0000001% of the market.  It looks like they have not introduced a new IC in about 10 years.  How did they get into this bind?

They saw that they couldn't compete with Altera and Xilinx and Lattice, and they didn't have anything specialist (rad-hard) like Microsemi, so they chose to stick with their core competency (processors, flash memory).
« Last Edit: October 07, 2015, 10:53:28 pm by Bassman59 »
 

Offline Bassman59

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #26 on: October 07, 2015, 10:52:23 pm »
For what chip? There is no generic Verilog or VHDL, all tools come only from a chip maker.

Hmmmm....,I see, so once you have made your choice and learned their version of VHDL language, then you are locked in to the chip vendor, right?

The languages are standardized. How well the vendors support the latest features of the languages in their tools is an issue, but for most designs it really doesn't matter.

What locks you into a chip vendor is when you choose to use the specialist hardware features of the chips, such as gigabit SERDES, clock management (PLL/DLL) and certain I/O features. In most cases those blocks are instantiated from a library, not inferred, so making code portable to another family is a challenge.
 

Offline uwezi

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #27 on: October 07, 2015, 11:06:26 pm »
I'm using also some old Lattice GALs - they are cheap and can be programmed in VHDL too (free IDE from Lattice). Programming GALs is a little problem - support in chinese programmers like TL866 is dubious (especially for GAL22V10, bigger are not supported) but the is always old good Galblast - requires old computer with 16-bit (I've not managed to run it on XP/7) but I've prepared USB bridge for Galblast hw with Arduino and simple command line app for 32-bit Windows.

Thanks, that was interesting! I still have quite a few vintage NOS and salvaged GALs lying around, but could not find any way to put them back into some use. You write that the support in the support in the TL8xx programmers is dubious - in which way?

I always found it annoying that Lattice kept their programming interface a secret - at least for private consumers. But I had built and used the Elrad(?) programmer on the parallel port at least for some projects, while I still had a DOS computer with a printer port... I suppose it should be possible to revive that one as well.

Are you willing to share your Arduino-interface?
 

Offline JoeN

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #28 on: October 07, 2015, 11:08:38 pm »
The only reason Atmel maintains FPGAs is contractual obligations. As soon as contracts expire, they will be gone in a jiffy.
Don't do any new designs using them.
That's what I thought.  They seem to have about 0.0000001% of the market.  It looks like they have not introduced a new IC in about 10 years.  How did they get into this bind?
Why do you see it as a bind? Markets change. You only get into a bind if you don't change with them.

I only meant to say they are in a bind on this one product line (PLDs).  They seem to be doing fine on microcontrollers, touch, and even small memories.
Have You Been Triggered Today?
 

Offline artag

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #29 on: October 08, 2015, 12:57:16 am »
No, they've somewhat lost it. They can make ARMs cheaper than they can make AVRs. I don't know why that is - perhaps they don't scale well to modern processes, or perhaps their hands are tied by some IP issues.

So Cypress and Dialog were arguing over who was going to take them over. That wouldn't have happened if they were healthy. It will be interesting to see what Dialog do with them.
 

Offline Kalvin

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #30 on: October 08, 2015, 06:45:27 am »
I would look at the small Flash-based FPGA devices. For example, you can get a small-size FPGA in less than $2:

http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/

Digikey prices for different iCE40-series FPGAs:

http://www.digikey.com/product-search/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/2556262?k=iCE40

No 5V tolerant I/O? Just add a cheap voltage level translator to each pin which requires 5V tolerant input or needs to be able to drive 5V output.
There are available cheap quad logic level translators which are bidirectional and can detect the direction automagically.

ice40 is NOT flash based. They use a NVM to store firmware, which is OTP. There are info saying they can store up to 4 configurations, and using cold boot pins to select which one to boot.

For multiple programming usages, they require external flash roms.

Thanks for correction! You are absolutely right. I didn't go through the datasheet carefully enough and assumed it to be Flash-based. The ice40 has an on-chip, one-time-programmable configuration memory (NVCM) which can be used to store the FPGA configuration once the device is ready for production. Thus, when the device powers up, it will load the configuration from the on-chip NVCM. However, the device can also boot from an external, standard SPI flash/eeprom which is very handy during development. The third option is to use the microcontroller to provide the configuration bitstream instead of the SPI flash/eeprom which allows in-the-field FPGA configuration updates. The iCE40LP, iCE40HX, iCE40 Ultra and iCE40 UltraLite devices can read only one bitstream from the external SPI flash/eeprom. The iCE40LP and iCE40HX devices can select one out of four bistreams stored in the external SPI flash/eeprom depending on the state of the two I/O-pins during the power-up.

http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/IK/iCE40ProgrammingandConfiguration.pdf?document_id=46502

Some manufacturers offer real Flash-based devices, which can be programmed multiple times and which do not require external memory of microcontroller to store the configuration bitstream.
« Last Edit: October 08, 2015, 07:09:04 am by Kalvin »
 

Offline helius

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #31 on: October 08, 2015, 07:04:51 am »
Some manufacturers offer real Flash-based devices, which can be programmed multiple times and which do not require external memory of microcontroller to store the configuration bitstream.
Besides Microsemi (née Actel) which are they?
 

Offline Kalvin

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #32 on: October 08, 2015, 07:23:51 am »
Some manufacturers offer real Flash-based devices, which can be programmed multiple times and which do not require external memory of microcontroller to store the configuration bitstream.
Besides Microsemi (née Actel) which are they?
Altera MAX10 and MAX V FPGA/CPLD families seems to be Flash-based.
 

Offline Kalvin

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #33 on: October 08, 2015, 12:20:17 pm »
They do have flash on fabric, but are they true flash based logic remains unknown to me. I used proasic3, and I can say that proasic3, igloo, fusion devices are flash based logic.

Altera MAX 10 has on-chip configuration Flash in addition to User accessable Flash blocks, according to the family datasheet. Some devices have even two configuration block to allow live configuration update. As far as I can read the datasheet, the devices are not hot at power-up, ie. it takes a few milliseconds from the device to read its on-chip configuration Flash and configure its logic fabric, and this needs to be taken into account on the system  design.

Altera's solution is quite similar to Xlinx's and others SRAM-based logic fabrics, except that the device contains one-time-programmable configuration memory, but it can also boot from the external SPI Flash memory similar to Xilinx and others.

Microsemi's Proasic3, Igloo and Fusion devices are hot at power-up AFAIK ie. the  device configuration is stored at the logic elements thus eliminating those a few milliseconds and the device is ready to rock&roll as soon asi it will be powered up.
 


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