Implementing a VHDL uart/acia

[Dajgoro]

Hi.

So I got the Mach X02 breakout board, and I am trying to get an serial com on it to work.
I've done stuff with Xilinx CPLD-s in the past with vhdl, but never something big enough that could support a proper included module.

I was looking for uart sourced on the web, but I couldn't not find any that was properly documented.
Later i found one that describes the MC6850 ACIA, which I actually used once, and it is simple to interface.
http://opencores.org/websvn,filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2FACIA_6850.vhd

But whatever I try, I just can't interface with it from the main vhdl source.
How do I port map the acia to my main design properly if I have a data, clock, and rx signal?

Edit: My main issue seems to be syntax, I tried looking into tutorials and examples, but I just can't get it right.

[Dajgoro]

Ok, i figured it out, here is a nice example:
http://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html

I was putting the declaration after the second begin, so it was an error.

But I still can't get the urat to reed a byte.

[Dajgoro]

I found another source, this one seems to work, still need to get tx working properly:

http://opencores.org/project,rs232_interface

[hamster_nz]

I think the conversation is quiet because you have told us what you are wanting to do (use a UART) but not why you want to do it.

Receiving and sending serial data isn't that hard on an FPGA, and unless you are using a soft CPU in your design it is most likely over-engineering the design. However, if you are using a soft CPU, then you should use the standard UART IP, so shouldn't have to engineer much at all.

For example, http://hamsterworks.co.nz/mediawiki/index.php/Log_Pins is to a (really crappy) design that logs the status of 11 pins as ASCII characters to a serial ports. And then http://hamsterworks.co.nz/mediawiki/index.php/PmodMAXSONAR is a (really shoddy) design that receives a few characters of RS232 data from a Ultrasonic range sensor.

[Dajgoro]

For now this is the entire project, I first want to get a proper uart operational, so once that works, I can go working on the rest of the project. There is no soft core for now, but I might use one later.

[hamster_nz]

I'm just a little confused, as a UART by itself doesn't do much.

What do you want to send?
What do you want to receive?
How are you going to send it?
What are you going to do do with whatever you receive?

Maybe those questions are a bit flakey... here are some more precise questions:

Will you need to buffer data in either direction? If so, how deep?
Do you need a fixed baud rate, or programmable baud clock generator?
Do you need to generate parity?
What stop bit options will you need?
Do you need to support seven data bits?
Do you you need to receive or send 'break's?
Do you need hardware flow control signals?
Do you want to implement automatic software flow control?
Do you need to support interrupts or can the interface be 8-bit data bus + data_enable signal in each direction?

If your answers are:
- No buffering for either RX or TX
- No parity
- Only 1 stop bit
- Only 8 data bits
- No need to receive or send breaks
- No hardware support for flow control
- Baud rate fixed at build time
- No interrupt signals needed

...then a UART most likely isn't the answer to your problem.

[Dajgoro]

If your answers are:
- No buffering for either RX or TX
- No parity
- Only 1 stop bit
- Only 8 data bits
- No need to receive or send breaks
- No hardware support for flow control
- Baud rate fixed at build time
- No interrupt signals needed

...then a UART most likely isn't the answer to your problem.

For now that is what I wanted, that is why I wrote uart/acia.
But later when developing a proper project, it would be nice to have those features.
As for buffering, that is not critical, since implementing my own buffer is not that hard.

[nctnico]

Xilinx has a very simple UART design. You could use Opencores to get some useful hints but beware a lot of designs on Opencores are not the best.

[legacy]

well, Xilinx has a pretty simple uart design in the pico blaze project.

[hamster_nz]

well, Xilinx has a pretty simple uart design in the pico blaze project.

... and the Xilinx licensing forbids them from being used on anything other than an Xilinx FPGA...

[K5HJ]

Here's another resource that might help:

http://www.fpga4fun.com/SerialInterface.html

Although, he refers to it as an RS232 interface, which it is not.

Randy

[Bassman59]

well, Xilinx has a pretty simple uart design in the pico blaze project.

... and the Xilinx licensing forbids them from being used on anything other than an Xilinx FPGA...

... and it's written in the style of directly instantiating LUTs with INITs, so it's pretty much obfuscated.

Having said that, a UART is something that is very trivial to write.

[codeboy2k]

There's an open source uart here, it's kinda hacky, in that it has no configuration, and hardcoded timing divisors for the uart clock (which you can easily change before you synthesize it.

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/blob/master/projects/VHDL_Xilinx_Port/uart.vhd

It is simple, and easy to understand in about 30 seconds.

[Dajgoro]

Both the github and the one form opencores have a txstrobe signal. How do I strobe a signal for just one clock period, without writing an entire contraption?

[codeboy2k]

Both the github and the one form opencores have a txstrobe signal. How do I strobe a signal for just one clock period, without writing an entire contraption?

I'm not sure I understand what you're missing about it.  I have not looked at the opencores version, but in the github one the txstrobe is an input, when it's set to high (by your code) and the transmitter is ready it will latch the input data into the internal register buffer, then send it out, bit-by-bit. While the bit banging is in process, it will keep the output txbusy high.  When txbusy goes low, you can strobe more data in with the txstrobe input.

So txstrobe (in) and txbusy (out) are your handshaking signals.

[Bassman59]

Both the github and the one form opencores have a txstrobe signal. How do I strobe a signal for just one clock period, without writing an entire contraption?

Well, that's the rub, isn't it? You can't just plop down the core without considering the entire design.

Say you want to transmit 20 characters. Your logic has to write those 20 characters to the transmitter. But the logic cannot overwrite what is already in the transmitter, so you need to manage the whole process.

No part of a design lives in a vacuum.

[hamster_nz]

Both the github and the one form opencores have a txstrobe signal. How do I strobe a signal for just one clock period, without writing an entire contraption?

Something like this (just typed into post, so sorry in advance for errors!):

Code: [Select]

clk_process: process(clk)
  begin
     if rising_edge(clk) then
        if busy = '0' and strobe = ''0' then
            -- Send a new character
            data <= "00110000"; -- ASCII for '0' to be sent.
            strobe <= '1';
        else
             -- do nothing as the TX is busy
            data <= "00000000"; -- ASCII NULL - never sent, but just for completeness.
            strobe <= '0';
        end if;
     end if;
  end process;

If Busy, Data and Strobe are connected to the UART it should output a continuous stream of ASCII zeros.