I have already posted, how an an ADC buffer might look like. The schematic just does not include the ADC input decoupling cap, which may be something around the few nF (1 to 3nF).
The cap there is there to decrease the output impedance of the buffer at high frequency (the sampling current pulses), and the circuit is wired so that the DC output impedance is zero, yet it is fully stable with that capacitive load.