Hi All, I have posted about this a while back but am now unable to find the original thread. I have just returned to this project after some time and this issue is still bugging the hell out of me as I was never able to resolve it.
It's a section on my function generator for calibrating the main on board frequency reference and provides an external counter via a ispMach 4000ZE cpld - specifically the LC4256ZE-5TN100C. I have attached the schematic below.
The tools I am using are the ispLEVER, Latice Diamond Programmer, and the official Latice HW-USB-2B programming cable $$$
ispLEVER builds my project fine (for the above device) and spits out the JED file.
The Latice programmer is able to complete the JTAG scan OK, verify the cpld device ID OK, but every time I program it the verification pass fails.
The output window shows this...
INFO - Check configuration setup: Start.
INFO - JTAG Chain Verification. No Errors.
INFO - Check configuration setup: Successful.
INFO - Device1 LC4256ZE: Erase,Program,Verify
ERROR -
Failed in Function VERIFY (see log file for more details)
ERROR - Process Operation Failed.
INFO - Elapsed time: 00 min : 01 sec
ERROR - Operation: unsuccessful.
ERROR - Programming failed.
And the log shows this...
Connected to Lattice Cable Server.
Lattice HW-USBN-2B cable detected.
Frequency setting= 2727272 Hz
Check configuration setup: Start.
Frequency setting= 2727272 Hz
JTAG Chain Verification. No Errors.
Check configuration setup: Successful.
Device1 LC4256ZE: Erase,Program,Verify
Frequency setting= 2727272 Hz
Frequency setting= 2727272 Hz
--------------Row1--------------:
HDR 0
TDR 0
SDR 1592 TDI(00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000)
Expected TDO(5FF87E0318C6318C619CEBFFFFFE3FFFE3FFC7F87FFFFDFFFEBFFF8BFF10842108421BD7FFF17FE2F884213FFF17FFFFFFBD7FFF1FFE7F9CE739DEFFAFFC3F18CC6318C6318C7DFFFFFFFAFFFFFFFC3F17C5F18CE75FFFC5FF8BE2108421085FFFFFFEF5FFFC1F098C6318C6318CBFFF8FFF3FCE77BDE37FFFFEFFFFEBFFF83E5318C6318C67B97FFF17FE2F8842117FF7FFFFFFFBD7FFF1FFE6F98E73BDEFFAFFFE6FFCDF318C6318C5FFFFFF7FAFFFE2FFC42109EF19FFF5FFFCFFF986739CE77BDFFFFFFFFD)
Received TDO(FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000)
Bits Error 1592: Expected: 0 Received: 1
Bits Error 1590: Expected: 0 Received: 1
Bits Error 1579: Expected: 0 Received: 1
Bits Error 1578: Expected: 0 Received: 1
Bits Error 1577: Expected: 0 Received: 1
Bits Error 1576: Expected: 0 Received: 1
Bits Error 1569: Expected: 0 Received: 1
Bits Error 1568: Expected: 0 Received: 1
Bits Error 1567: Expected: 0 Received: 1
Bits Error 1566: Expected: 0 Received: 1
and more...
Execution time: 00 min : 02 sec
Failed in Function VERIFY (see log file for more details)
Process Operation Failed.
Elapsed time: 00 min : 02 sec
Operation: unsuccessful.
The fact that the device ID comes back OK makes me think I have no problem with the cable connections to the chip or the power to the chip? I have tried the custom Clock Divider = x10 but same thing.
I feel that since the Device ID verifies without issue that I have at least validated the connections (TMS, TDI, TDO, TCK, VCC & GND) ? Or is that being optimistic?
The issue is I have never been able to load and verify the JED file to the device?
I would really really like to hear from others who have used any of the above tools and had any similar issues that might help me out.