I can't set a top-level unit by right-clicking either, the option is grayed out. In the couple of months I've been using Lattice I've never had it select the wrong thing as the top level when everything else was working fine, but I'll keep that in mind.
This does not just effect a single project, this is affecting my entire lattice no matter the project I open it's the same. It really feels like this is just a setting somewhere that I somehow turned off or on (although the not being able to set top level is very odd).
I can simulate and synthesize, and both will compile and tell me my errors. Everything is mapped fine after synthesis, the netlist all looks like it used to, and the time analysis is the same as it should be. Simulation of my program works as before, selecting the correct top level entity itself, and I was just entering the testing in the real world phase of my project so my code running on my FPGA does not currently work however I'm pretty sure it I will be able to get it to work once I correct my minor circuit/programming error. If I change my program, the simulation changes with it, so it's not as if it's not saving or anything like that. Technically speaking, all the parts of the program that seemed to "break" weren't vital, especially since I'm at the bug testing phase right now and there's not much code left to write. However, not being able to check my code over without synthesizing or simulating is getting rather tedious, and not being able to see what entity is the top level is a bit of a concern (although when I simulate it opens all my files up in multi-sim and prompts me to select the top level entity, so again there are work arounds I can find).