Actually the error message is clear about it:
@E: CS168 :"/home2/Develop/fpga/icecube/quad/quad.v":85:10:85:10|Port CLKHF_EN does not exist
But CLKHF_EN is mentioned in one of their hundreds docs about iCE (o;
Here is the whole design (where rgb out is stuck at 1 driven by internal oscillator):
The same design runs perfect on a MAX1000.
module quad
(
quadA,
quadB,
rgb,
push
);
input quadA, quadB, push;
output rgb;
reg [2:0] quadA_delayed, quadB_delayed;
reg [2:0] pushA_delayed, pushB_delayed;
always @(posedge hfclk)
if(push)
quadA_delayed <= {quadA_delayed[1:0], quadA};
else
pushA_delayed <= {pushA_delayed[1:0], quadA};
always @(posedge hfclk)
if(push)
quadB_delayed <= {quadB_delayed[1:0], quadB};
else
pushB_delayed <= {pushB_delayed[1:0], quadB};
wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];
wire volume_enable = pushA_delayed[1] ^ pushA_delayed[2] ^ pushB_delayed[1] ^ pushB_delayed[2];
wire volume_direction = pushA_delayed[1] ^ pushB_delayed[2];
reg [7:0] count;
reg [7:0] volume;
wire rgb;
always @(posedge hfclk)
begin
if(count_enable)
begin
if(count_direction)
begin
if (count < 165)
count<=count+1;
end
else
begin
if (count > 0)
count<=count-1;
end
end
end
always @(posedge hfclk)
begin
if(volume_enable)
begin
if(volume_direction)
begin
if (volume < 191)
volume<=volume+1;
end
else
begin
if (volume > 0)
volume<=volume-1;
end
end
end
ws2811 rgb_ring (
.wsclk(hfclk),
.reset(1'b0),
.DO(rgb),
.red_in(count),
.green_in(count),
.blue_in(count),
.volume(volume)
);
SB_HFOSC OSCInst0 (
.CLKHF_EN(1'b1),
.CLKHF_PU(1'b1),
.CLKHF(hfclk)
);
endmodule
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