Lattice IceCube Creating a clock

[bentomo]

Hey guys,

so I'm using a lattice ice40HX8K and I have an open source project implemented that I need to now modify. Basically someone was using a lattice part and said they were decent fo the price, and I picked up an ice40 not realizing that the tool chain is pretty bonkers for this line.

The current design is being driven by an external clock but I want to use the internal PLL to generate another clock and run it off the board to a TFT LCD. If I use the PLL configuration tool it basically asks me for an input pin and an output pin, as if there's no internal OSC. It also creates them in verilog synthesis files, but my top level is written in VHDL so I'm not sure how to add this.

So does anyone know how to create and implement a 40MHZ clock with this tool chain?

[bentomo]

Thanks, it looks like I'm getting on the right track.

I was able to use the pll module generator to take my input 54mhz clock and create a 40mhz clock. I also figured out that you can just select the file type when you're saving to be .vhdl and it will give you the vhdl component.

Now I just need to figure out how to instantiate it. I feel like if I just instantiate it as if I included a library I should be able to but synplify pro synthesis complains that it's an undefined identifier.

More to work through I suppose.


EDIT: Ok I believe I figured it out. I won't know until I load it onto the board and confirm

When you've gotten to the end of the PLL module generator tool you can save in verilog or VHDL. Pick your poison here.
But when you save it will save 3 files not just one. The first is the module itself, you'll need to add this to your design source files. The second is an example of how to instantiate it into your design, not really needed but ok. The third is a .lpc file. I'm not sure what this is for but it sounds like an ice40 specific constraints file. I didn't need to include it but I left it in my directory.

Following the rather vague instructions from the ice40sysCLOCKpllDesignandUsageGuide
1. include the module in your component libraries
2. Instantiate the component into your top level and hookup your input clock, output signal, and reset if you want one

In hindsight this process is pretty straight forward so I can't complain too much. The documentation is there for how to use the PLL module generator, just not for what files are generated. I have some fpga experience so I feel like it shouldn't have taken me 3 hours to figure out how to put the pieces together.