I am using a Lattice iCE40 Ultra FPGA which has 2 hardened SPI and 2 hardened I2C busses and I was kind of surprised to see a hardened SPI bus. A SPI bus can be as simple as a shift register driven by the SCK pin - and I feel like it is easier to just write your own IP, than it is to figure out the register structure of their implementation and use theirs. (I2C has weird things like clock stretching which sounds annoying to implement so I am focusing on SPI).
Reasons I can see for using their IP:
- If you want it to work with unknown third party SPI devices so you have to make sure that the standard is fully implemented
- You have multiple masters and need to handle bus arbitration etc.
However, I expect that the majority case is using a SPI bus with only a single master and known slaves (with known features) and in this case it seems easier to write my own bus controller. My application uses a single Master and Slave to transfer an image between devices.
I guess my question is - am I overlooking something? Am I being lazy by not properly learning how to use their IP? Would you write your own or use theirs?
Here is their SPI IP usage guide:
http://latticesemi.com/view_document?document_id=50117