Author Topic: Lattice MachXO2 breakout board - is it possible to replace FPGA with different?  (Read 2401 times)

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Offline Brane212Topic starter

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I have two such boards. Originally both were with XO27000HE chip, but I managed to let magic smoke out of one, so I replaced it. BUt because Farnell didn't have HE version, I used HC instead and adapted VCC from 1.2V to 3.3V. Basically I bricked two Vccx testpoints together and so now I have 3.3V for I/O and core.

New chip seem to be soldered on correctly, but I can't program it through FTDI ( haven't checked ISP cable yet).

When trying to program basic demo ( blinks LEDs), it fails with:

Quote

    Device#1 LCMXO2-7000HC: Failed to verify the ID
    (Expected: 0x012BD043 Read: 0xFFFFFFFE).

    ERROR - Check configuration setup: Unsuccessful.

    ERROR: pgr_program failed.

    ERROR - Programming failed.


I suspect FTDI's EEPROM might be the possible issue- that it expects HE version.

I noticed that those boards tend to carry different chips- early ones were with XO2-1200HE
Do they have to be tweaked (EEPROM) or should this just work and I screwed something else ?
 

Offline janoc

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The FTDI EEPROM is unlikely to be a problem - it only stores things like USB VID/PID for the FTDI chip. The USB bridge certainly has no clue about what it connected to it and not much intelligence. It knows how to do JTAG or SPI when you send it specific USB packets, but that's all. The rest of the smarts is in the host software.

That failure looks like the chip isn't talking at all to the FTDI. Are you sure the HC and HE versions have the same pinout?
 
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Offline Brane212Topic starter

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YEAH ! It works now !

I don't know how I managed that, but I somehow have cut TDI line just above ISPconnector an  thus have cut from the FPGA both ISP and FTDI.

Cut was done inadvertently with something as sharp as Xacto knife and cut was more like a stab over track and was practically invisible.

After this was taken care of, thing started working. Only thing I did was to remove R56 (bridge for Vccio) and connect 3.3V to its FPGA side, leaving 1.2V line intact to be used perhaps for something else or reworking it with adjustable regulator.
 


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