Lattice PLL settings

[Dajgoro]

Hi,

I'm trying to get the PLL in the XO2 - 7000 working properly, but I'm having some odd issues.
On page 24: http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/MO/MachXO2sysCLOCKPLLDesignandUsageGuide.pdf?document_id=39080
It is shown the PLL config window, and whatever settings I type in there the frequency I get out is about 10x less than what the dialog shows.
So if I set 100 and if it says "actual frequency" to be 100 as well, I see 10Hz on my scope. What could be causing this.
The PLL pins are directly mapped to the output pins, there is no other HDL code.

[iMo]

What is your CLKI frequency?

[Dajgoro]

What is your CLKI frequency?

I'm actually not sure, I did not set any settings for it, so it must be some sort of default value.
How do I access the settings for the CLKI?

[iMo]

CLKI is the input clock you feed a PLL module with, such you get a CLKOP  out of it.
PLL module only multiplies the CLKI by X.

You have to connect an external oscillator (3.3V level) to the CLKI, or use an internal clock source, if any, and connect it to the CLKI.

In the configurator you have to input the actual CLKI frequency, for example 20MHz.

[Dajgoro]

If I did not connect any input clock, why is it working at all.
I will look into that, try to give it a proper clock source.

Also why at certain frequencies some division ratios are not possible, for example divide by 15 only works at less than 60?

[iMo]

Best is to read the app notes..