As the new "Lattice Radiant" development system tailored for the iCE40UP3k/5k series has been mentioned briefly in other topics let us start a separate thread..
I've spent a few days comparing a verilog design (j1a cpu) under IceCube2 and Radiant. They changed the names and parameter's formats with all primitives in Radiant, thus you have to migrate an existing design from the IceCube2 (or IceStorm) to the Radiant first. It requires a lot of reading, however
As an example I've compared the building of an "identical verilog
design" under IceCube2 and Radiant - a j1a (forth) cpu utilizing all bram and spram and 27 pins, running at 24MHz w/ internal oscillator (iCE40UP5k UPduino board):
Tool Size(LUTs) Time to build maxClk est. [MHz]
==========================================================
IceCube2 2703 2:56 35 (34-36)
Radiant 2741 3:30 19 (15-20)
Note: time to build is +/-10secs, SynPro w/ default IceCube2 and Radiant setup, ring-osc commented out.
The Radiant provides rather conservative timing's estimates (similar to the IceStorm's ones), while IceCube2 is always pretty optimistic.
On silicon the Radiant binaries with 15-17MHz max clock
estimates are not working properly, thus it seems the Radiant provides
much more realistic estimates.
Some first glance findings:
1. The Radiant offers a new INV primitive, therefore I've tried to create a ring oscillator made of 3 INVs (a part of a random generator). It does not synthesize with SynPro, it does with LSE (and it works on silicon).
Edit: Tech Support proposed a workaround, it works.
2. The Reveal Analyzer inserts an JTAG module into your design (together with an LA) - here the synthesis stops with an error indicating an unknown primitive "INV_c" wired in jtck signal.
3. The Reveal Analyzer knows the FT232H
INFO - cable[0]=FTUSB-0,USB2,Single RS232-HS Location 0000
The logic analyzer has not been tested yet, see point 2.