Length Tuning and vias

[luiHS]

Hi.

I have made a first PCB design with Length Tuning, for the tracks that go to an SDRAM connected to an RT1020 Cortex M7 500Mhz microcontroller.

I'm not sure I calculated it well.
To calculate the total length of the track, do we have to count the thickness of the PCB when there are vias on that track?

In the screenshots attached, there are some tracks that go all on the TOP side without vias, and the others go on the Bottom side, with vias on the pins of the SDRAM, and vias on the pins of the Microcontroller.
For tracks with double via, I subtracted to the length of the track, 3.2mm (1.6mm thickness of PCB for each via).

Is this correct ?
I do not think Eagle automatically calculates it, because I have not seen Eagle request it.

Anyway, I'm beginning to suspect that the track length of the data bus does not have to be tuned to the track length of the address bus, but they have to be the same length for each bus, but I'm not sure.

Nor is it clear to me if the control lines should be tuned to each other, or also to the same length as the bus tracks.

[jmsigler]

I can't speak to this particular interface, but to account for the via length you would add 2 times the board thickness to the trace length (i.e. the top traces would need to be a bit longer obviously). I'd guess that for an interface with this speed you don't need to worry about the length of the vias, They add ~17pS of skew between this signals, which you could get away with even with a moderately fast DDR3/2 interface.

[luiHS]

 
This is the scheme of the evaluation board, with the SDRAM connected to a micro RT1020. What I do not know is that all those 0 ohm resistors connected in serial with the buses and the control lines are used.

On the board, they appear connected in serial, but halfway on each track. I see on the evaluation board, that there are many tracks that go in parallel.

The last photo is from the bus that goes on the bottom side.

[Kasper]

Those 0 ohm resistors might be placeholders for emi compliance tuning. If the circuit emits too much then those can be changed to 100 ohm or whatever is needed to reduce the emissions. It creates an RC LPF with the parasitic capacitance of ICs etc. That cuts out high frequency noise that can be emitted from fast rise/fall time on the data signals.

When feasible, use the same amount of vias in each matched trace.

[NorthGuy]

At 166 MHz, the interval between clock edges is 3 ns. Relative to 3 ns, a several ps error is insignificant, so any reasonable estimate for vias will do.

[cgroen]

LuiHS,
nice to see a i.MXRT design! I have my first RT1062 (RT1064 once the chip is available) design finished and running 100% perfect.
I length matched the SDRAM signals to within 3 mm max difference which is WAY overkill, after all I'm only running 160 MHz clock on the SDRAM. The RT devices are laid out so that the pins are grouped almost perfectly for SDRAM etc. Wonderful little device!
I have 2 other designs currently waiting for PCB to arrive from China (JLCPCB), one board with Ethernet and some stuff, and a testboard with HyperRAM. I like the HyperRAM as it will free a lot of pins on the CPU....
Anyway, not an answer to your question, I was just thrilled to see some i.MXRT activity
Good luck on the project!

[luiHS]

LuiHS,
nice to see a i.MXRT design! I have my first RT1062 (RT1064 once the chip is available) design finished and running 100% perfect.
I length matched the SDRAM signals to within 3 mm max difference which is WAY overkill, after all I'm only running 160 MHz clock on the SDRAM. The RT devices are laid out so that the pins are grouped almost perfectly for SDRAM etc. Wonderful little device!
I have 2 other designs currently waiting for PCB to arrive from China (JLCPCB), one board with Ethernet and some stuff, and a testboard with HyperRAM. I like the HyperRAM as it will free a lot of pins on the CPU....
Anyway, not an answer to your question, I was just thrilled to see some i.MXRT activity
Good luck on the project!

What thickness of track and distance between tracks have you used, for the tracks that go from the microcontroller to the SDRAM?

I have been reading things about the impedance, which must be about 50 ohm, a user has recommended a distance between tracks of 20mil. Looking at the NXP evaluation board under the microscope, I would say that they use a track width of 6mil, and separation between tracks may double, over 12mil.

I have also ordered my boards to JLCPCB, they arrive in a few days by DHL, and I can already mount my first design with RT1020 LQFP144. I have got 26 samples that sent me NXP, because the LQFP144 is still not available in the distributors, although it was announced for the last quarter of 2018. In the Chinese it has been offered to me.

[luiHS]

Those 0 ohm resistors might be placeholders for emi compliance tuning. If the circuit emits too much then those can be changed to 100 ohm or whatever is needed to reduce the emissions. It creates an RC LPF with the parasitic capacitance of ICs etc. That cuts out high frequency noise that can be emitted from fast rise/fall time on the data signals.

When feasible, use the same amount of vias in each matched trace.

About those resistors a user said me:

" Those are the famous series termination resistors. If the signal is unidirectional, they go as close to the source pin (which emits the signal), if they are bidirectional, they go in the middle. These resistors are to improve the response of fast signals, decrease the overshoot for example.

There are tools that allow you to analyze this during the design, such as hyperlinx, but you leave the footprint for the resistors and evaluate it later. Generally they are resistors between 10 and 20 ohm that are placed.

Ahh and also your net has to have an impedance Z0 of 50 ohm, this depends on the distance to the inner plane and the thickness of the track. "

[cgroen]

What thickness of track and distance between tracks have you used, for the tracks that go from the microcontroller to the SDRAM?

I have been reading things about the impedance, which must be about 50 ohm, a user has recommended a distance between tracks of 20mil. Looking at the NXP evaluation board under the microscope, I would say that they use a track width of 6mil, and separation between tracks may double, over 12mil.

I have also ordered my boards to JLCPCB, they arrive in a few days by DHL, and I can already mount my first design with RT1020 LQFP144. I have got 26 samples that sent me NXP, because the LQFP144 is still not available in the distributors, although it was announced for the last quarter of 2018. In the Chinese it has been offered to me.

I use 5 mil traces and 5 mil spacing. I selected the JLC2313 stackup from JLCPCB, this should give 53 ohm (single ended) (again, overkill in this design)
Also I used VIA's that violated JLCPCB's capabilities (0.2mm hole, 0.35 mm outside diameter) but no comments on that from them and the PCBs were just perfect and worked very nicely.

From their calculator:

Single ended:
JLCPCB JLC7628 stackup:
4 layer, outer layer, 50 Ohm single ended: 11.55 mil trace
JLCPCB JLC2313:
4 layer, outer layer, 50 Ohm single ended: 5.8 mil trace

Differential:
JLCPCB JLC7628 stackup:
4 layer, outer layer, 100 Ohm diff: 8mil space, 8 mil trace
JLCPCB JLC2313:
4 layer, outer layer, 100 Ohm diff: 8mil space, 4.8 mil trace