looking for a fpga board with LVDS interface for big LCDs, 11inc-14inc

[legacy]

so, the autum is coming, the weather is bad (it's still raining here, four days of rain, I am going to buy a pair of fins) and I am currently very busy on a project which has absolutely nothing to deal with LCDs, but ... probably due to the bad weather ... my customer is already talking about the next step and 

and probably I will end dealing one of those unfriendly ultra high speed design LCDs, e.g. 1024x768 pixel x nbit-color x60Hz = an horror movie on the hardware & timing side as well as on signal integrity, since It goes like a bandwidth of 200Mhz and probably it will double the double when the customer will ask to increase the resolution.

I am a bit worried about it. Really.
More worried than the need to buy a pair of fins to reach my desk.

My default answer is already set into "absolutely no! I can't do it, sorry"
But he will probably force me to do it, and he is very good at persuading people.

So, the question is: is there an eval board with an LVDS interface and a well documented LCD?

Just to have something to get started 

[Buriedcode]

Does it have to be LVDS?  I may be missing something here, but surely you could settle for HDMI and a zynq board?

[legacy]

Does it have to be LVDS?

Basically the same LCDs used in laptops.
Thus no HDMI, VGA, etc.
You have to directly interface the big-LCD.

[legacy]

(laptop LCD panels do not provide an HDMI, DVI, or VGA interface, as they are intended to be wired directly into the laptop's graphics controller ... that is where my problem begins since I will probably be the one doomed to design the graphics controller with fpga)

[nctnico]

Does it have to be LVDS?

Basically the same LCDs used in laptops.
Thus no HDMI, VGA, etc.
You have to directly interface the big-LCD.

Even a Spartan6 has serializers/deserializers in each IOB (input /output block) so generating LVDS at high rates is pretty easy. I don't see the problem at all! Connect a DDR memory to it and you have dual port memory at IIRC 3GB/s. Driving a full HD screen 24bpp @60Hz is easy.

[legacy]

200Mhz of signal (when not 400Mhz). At least.
On a cable long 20cm. This IS the problem.

Also, do you have documentation for LCD panels?

[Ice-Tea]

LVDS is quite forgiving in my experience.

Drove WUXGA panels with a Stratix I ES 15 years ago. From an ETX board, to a carrier card, over a cPCI connector to a backplane, from the backplane over cPCI to another board, passive loop through there, back to the backplane, /*repeat twice*/ the end.

Not much of an issue, me thinks. From back in the day, I remember deserialisation with a factor of 7 was a bit of an issue but I guess that should be easy peasy nowadays...

[stmdude]

I'm not completely up to snuff on the display-stuff, but I was under the impression that most laptop-screens are eDP these days, and not "LVDS".

eDP is similar enough to HDMI that you should be able to use that for testing

[legacy]

eDP is similar enough to HDMI that you should be able to use that for testing

it's still raining, and the sky is very dark, but this news sounds like a ray of light
let's check it out

[nctnico]

200Mhz of signal (when not 400Mhz). At least.
On a cable long 20cm. This IS the problem.

Also, do you have documentation for LCD panels?

You can download the documentation for any TFT panels to get the timing information. There are 2 schemes for putting the RGB+sync signals into the stream though: NS (national semiconductor) and JEIDA. NS is used the most. 20cm is no problem at all with LVDS. I've used 50cm cables on full-HD screens.

[legacy]

so, the phy side of the fpga has to do this for the lcd. 3.5X PLL 

[legacy]

Bypassing the LVDS chip (can't hack the lcd) is definitely the easiest way to go, but ...
... but using the LVDS bus has the advantage of reducing noise and requiring only 8 wires instead of 21 

[nctnico]

You can also opt for having an external LVDS serialiser to which you feed the parallel data + sync signals from the FPGA.

[legacy]

Which LVDS serialiser chip do you suggest ?
(the above in the link by TI is not suggested for new projects)

[nctnico]

Which LVDS serialiser chip do you suggest ?
(the above in the link by TI is not suggested for new projects)

Since TI has borged National Semiconductor they have the entire range to pick from. What you need is a serialiser which can deal with the pixelclock and width of the RGB bus. For full HD you'll likely need to be able to deal with a pixelclock of 2000x1200x60=144MHz-ish.

[legacy]

I am a bit surprised that such a boards don't exist ... bah ...
and, as usual, I need to put the "hardware-guy" hat on my head

anyway, thanks for advice 

[simmconn]

Actually any FPGA boards with differential IO signals routed to a header would work for your application. On the Xilinx Spartan 3A starter kit, there are LVDS capable headers on bank 0 and bank 2. On the digilent boards, look for 'high speed PMOD' interface. I think most Spartan 6 and later boards have them. Everyone uses a different connector for LVDS. The generic eval board can't predict what connector you use, hence the 0.1" headers.

Like nctnico said, the Spartan 6 and later integrated the serializers in the IOB, so it is quite easy to implement an LVDS interface from parallel RGB. Just follow the coregen wizard. The spartan 3A is a bit more complicated, but Xilinx has a reference design for it. We were able to drive a full-HD panel using two instances of the LVDS transmitter from that reference design. It took some minor tweaking to get it to work but is overall quite robust.

I haven't used the Altera much lately. I'm sure they also have differential signals routed to the headers on the eval boards. Starting from Cyclone IV they want either 2.5V IO or external resistor networks on the LVDS signals (don't remember which one), that's why I stayed away.