Ok so I am at another brick wall, I am now trying to do a simple PWM Driver (not completed yet, will eventually have multiple PWM outputs), I have a PWM module, a shift register input for serial data, and a top level to tie it all together, problem is when I try to compile it I get the design does not contain any logic, no errors or warnings otherwise other then the fact that I have no license for parallel compiling, why?
module PWMMAIN;
reg sclk;
reg clk;
reg latch;
reg sdata;
reg reset;
wire p0out;
reg [11:0] p0data;
wire [5:0] pwmAddr;
wire [11:0] pwmData;
PWM p0 (.clk (clk),.reset (reset),.data (p0data),.out (p0out));
SHIFTIN sd (.sclk (sclk), .latch (latch),.data (sdata), .addr (pwmAddr),.data_out (pwmData));
always @(posedge latch)
p0data <= pwmData;
endmodule
module PWM(clk,reset,data,out);
input clk;
input reset;
input [11:0] data;
output out;
reg out;
reg [11:0] pwmclk;
always @(posedge clk)
if (reset) begin
pwmclk <= 12'b0;
end else begin
if (pwmclk < data) begin
out <= 1;
end else begin
out <= 0;
end
pwmclk <= pwmclk + 1'b1;
end
endmodule
module SHIFTIN(sclk,latch,data,addr,data_out);
input sclk;
input latch;
input data;
output [11:0] data_out;
output [5:0] addr;
reg [5:0] bitCount;
reg [5:0] addr;
reg [11:0] data_out;
always @(posedge sclk or posedge latch)
if (latch) begin
bitCount <= 0;
end else begin
if (bitCount < 5) begin
// Address
addr <= addr << 1;
addr[0] <= data;
end else begin
// Data
data_out <= data_out << 1;
data_out[0] <= data;
end
bitCount <= bitCount + 1'b1;
end
endmodule
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