LVDS interface between ADC and FPGA

[gauravmp]

Hi,

I'm wondering if anyone can provide with a design example for an LVDS interface between an FPGA and an ADC. Specifically, I'm using a MAX 10 FPGA and an LTC2311 ADC.
Also, could someone give me a way to implement the interface by just using shift registers.

Any help would be appreciated.

Thanks.

[Scrts]

For 5Msps you can easily use single-ended IO. On the other hand, you can accommodate two LVDS pairs: one for transmitting (look for LVDS TX) and one for receiving (LVDS RX). Most of the LVDS pairs are capable of receiving.
You need to provide LVDS levels and exact MAX10 part number for more information.