LWMESH-OQPSK 1000kbps

[ataradov]

I have tested with two boards in the basic mode.Node-1 will send at 20 ms and Node-2 at 40ms from the time of  Sync command received. It seems to be working. Can you have look at the attached Wireshark log ?. 

If it works, it works. What is there to look at?

1. Is there any Wireshark protocol for Basic mode?. Because wireshark fields like Info,Protocol,Source and Destination gives different name while capture.

In basic mode, you define payload. So unless you write a dissector for your protocol, Wireshark will not know how to deal with it. Just use raw IEEE 802.15.4 frames and parse things manually.

[muthukural001]

Hi Ataradov,

Thanks.

Just use raw IEEE 802.15.4 frames and parse things manually.

I have to do this in the basic mode itself right?

[ataradov]

You do this in Wireshark. Basic mode is an internal thing to the radio. Wireshark does not care how your radio generated the frame.

[muthukural001]

Hi,

Q1:how to get start with writing dissector ?


Q2:How long it would take for developing Own protocol in wire shark?



Thanks,
Muthu

[ataradov]

Q1:how to get start with writing dissector ?

I have no clue. I have never written one. I bet they have some documentation on this - google it.

Q2:How long it would take for developing Own protocol in wire shark?

Writing itself is probably not that hard. But it will take some time to set up the build environment with all the dependencies and stuff.

You probably just want to download the source code and try to build it. If you don't want to publish your changes, then you can just hack up LwMesh dissector to show the data you want.

[muthukural001]

Hi Alex,


I am seeing problem when two external interrupts(ADC int and RF module int) starts to work.

Problem:

When I test without Gateway board, I can read the expected TEMPRATURE values from ADC in interrupt mode as there is no SYNC command sending and RF module interrupt will not trigger as well. The moment when I turn on Gateway board, RF module interrupt triggers whenever it send & receive  but ADC temperature values read as zero instead the expected value. couldn't come out of this even if Gateway board switched off again. It is going fine in to ADC handler.
 
Here is the code:

ADC Handler

Code: [Select]

int32_t volatile Tsample;
int32_t sample;
volatile bool adc_int=false;
void ad7124_irq_handler(void)  //ADC handler
{
adc_int=true;
struct system_pinmux_config pin_conf;
pin_conf.mux_position = 0x03; // Change MISO/EXTINT pin MUX position to Sercom MUX for SPI
system_pinmux_pin_set_config(PIN_PA04, &pin_conf);
ATOMIC_SECTION_ENTER
ret=AD7124_ReadData(ad7124_handler, &sample);
ATOMIC_SECTION_LEAVE
}

main

Code: [Select]

int main(void)
{
enum ad7124_registers regNr;
irq_initialize_vectors();
system_init();
delay_init();
configure_spi_master();                                 //ADC spi innterface at 3MHZ sclk
ret = AD7124_Setup(ad7124_handler, AD7124_SLAVE_ID, (ad7124_st_reg *)&ad7124_regs); //ADC functions
if (ret<0)
{
return;
}
ret= AD7124_Calibration(AD7124_SLAVE_ID);                                            //ADC functions
if (ret<0)
{
return;
}
for(regNr = AD7124_Status; (regNr < AD7124_REG_NO) && !(ret < 0); regNr++)           //ADC functions
{
ret = AD7124_ReadRegister(ad7124_handler, &ad7124_regs[regNr]);                  //------------------>Read Register value after Writing
if (ret < 0)
return;
}
port_pin_set_output_level(EXT1_PIN_10,false);
PHY_Init();
NWK_Init(SRC_ADDR);
timer_init();
appInit();
configure_extint_channel();
adc_irq_init((FUNC_PTR)ad7124_irq_handler);   //Pointing ADC handler
cpu_irq_enable();
port_pin_set_output_level(EXT1_PIN_10,true);  //start conversion
    while (1)
{

               if (adc_int==true)
              {
          adc_int=false;
          struct system_pinmux_config pin_conf;
          pin_conf.mux_position = 0x00;        // change back MUX position to EXTINT to detect next RDY
          system_pinmux_pin_set_config(PIN_PA04, &pin_conf);
          ATOMIC_SECTION_ENTER
          Tsample=sample;
          ATOMIC_SECTION_LEAVE
          channelnum= Tsample & 0x0F;
          if(acqptr<50)                                            //Buffer capacity for 10 samples (50 bytes)
         {
acqbuf[acqptr++]= MODULE_NO;                     // MODULE_NO as per Lab view configuraion
acqbuf[acqptr++]= channelnum;
acqbuf[acqptr++]= (Tsample>>24) & 0xFF;
acqbuf[acqptr++]= (Tsample>>16) & 0xFF;
acqbuf[acqptr++]= (Tsample>>8) & 0xFF;
                  }
                  if(acqptr==50)
         {
acqptr=0;
                  }
}
Suggest.


Thanks,
Muthu

[ataradov]

I don't know. Debug!

[muthukural001]

Hi Alex,

I successfully sent ADC packets from two boards to Receiver in time sync method without loss. I want to know something in the code,

There is nwkSyncAck, When I send sync command, I assign the value of nwkSyncAck which is modified by the last node acknowledgement to nwkSyncCmd.ack. But in the node side, it is not used for any purpose.

Also

Code: [Select]

if ((counters[ind->src] + 1) != data->counter)
{
SYS_CTRL_LOG = "Counter mismatch"; //in the shared code
}
Should I use the above code in the NWK_DataInd function?

Thanks,
Muthu

[ataradov]

It is basically a combined ACK variable for the whole time frame, you are free to use it however you like.

[muthukural001]

Hi Alex,
Everything is going in the right way. But, I see the slot Timer interrupt occurence at 5-10ms tolerance from the slot period set. I set slot time for 20ms. First node will trigger at 20ms, second node at 40ms and third one at 60ms. But realistically, first node trigger at 24 ms, second node at 46msand third one at 72ms from the time of SYNC command received with the following board clock.

     (Internal oscillator)OSC32K--------------->SYSTEM_CLOCK_SOURCE_DFLL---->48MHz, with Closed-loop

Please suggest a solution...


Regards,
Muthu

[ataradov]

Configure GCLK output on a pin and measure the actual clock frequency.

And them double check your timer configuration.

[muthukural001]

Hi,

Ok, I can guess that Measuring the clock and apply it to the following formula which is used to calculate period,

(F_CPU / 1000ul / 256) * i; //F_CPU=Actual clock frequency

........


Coming to the Range,

Case-10ft distance:
I checked with 3 transmitters to the Receiver which is 10 feet away from the transmitters...In this case, for sometime I get 100% reception from each transmitters and sometime I see losses which is negligible...

case-30ft distance:
This one gives poor output... I see 10-30% losses from each of the transmitters...


In the field, Receiver will sit at 100ft away from transmitters....suggest


Regards,
Muthu

[ataradov]

Ok, I can guess that Measuring the clock and apply it to the following formula which is used to calculate period,

Well, not really. You need to understand why  they clock is so wrong compared to the requested. You are talking about huge differences.

In the field, Receiver will sit at 100ft away from transmitters....suggest

Perform actual measurements with actual instruments. Something is wrong with your hardware, I don't know what.

[muthukural001]

Hi Alex,

I measured Main clock in the closed loop as well open loop. In the closed loop mode, clock oscillate between  47-48.5MHz.For open loop mode, it is between 44 - 45.1MHz.....

 GCLK_GENERATOR_1 source is internal 32Khz oscillator... Electrical characteristics says it may vary between 32.572 to 33.044 kHz at room temperature and 3.3V VDD...


Please look at the oscilloscope images for Open loop and closed loop mode... I am not able to figure out why it happens ....Please suggest how to get stable clock..........


Thanks,
Muthu

[muthukural001]

Hi Alex,


I tried with 16MHZ internal oscillator as source for GENRATOR 1 with the pre-scalar of 500... since it has less variation in output frequency.

As input reference should be between 0.732 kHz to 35.1 kHz, I am dividing 16MHZ with 500 to get 32KHz..

In the DFLL configuration, I set DFLL_MULTIPLY_FACTOR to 1500 so that 1500*32Khz=48MHz.....

After done this, I see that timer triggers +/-1ms from the expected value...I don't see much difference which I saw with the Internal 32k input to DFLL.....

give your comments.


Reagrds,
Muthu

[ataradov]

That all sounds about right. You can also put your 32 kHz source on the output, just to verify its actual frequency.

1 ms for short-term delays is still a lot.

Open loop mode depends on your setting of the tuning values, so it can be anything.

[muthukural001]

Hi Alex,
I will do that..

Is there any way to set the required frequency by using Internal oscillators? (OR) Should I use external oscillators which have <=10ppm as source to generate 48MHz ?

Is there any documents which solve the above?


Thanks,
Muthu

[ataradov]

Internal RC oscillator is plenty accurate. You just need to trace things on each step and verify all frequencies. Make sure that division and multiplication factors are correct, etc. You are measuring very short time intervals.

External oscillators are preferable, of course, but 10 ppm is probably an overkill, 25 ppm should be sufficient.

[muthukural001]

Hi Alex,
Thanks..I recheck internal oscillator configurations...

Now,the biggest problem for us is that getting range....

RF MOULE:
We are using the available off-the-shelf 212B module board from Atmel/Microchip.

Antenna:
Coming to the antenna, we didn't design it. We are using off-the-shelf antenna..Here, we have to connect the antenna cable to module connector only..

Antenna information:

Antenna used for our custom board is :
Mfg:66089-0906
Des: ANTENNA U.FL 915MHZ 6MM -3dBi



Can you recommend antennas for 915 MHz ?

Suggest..

Thanks,
Muthu

[ataradov]

I don't have a lot of hands on experience with sub-GHz, so I can't recommend much apart from performing basic measurements on your system.

I'd download a copy of  FCC tester from atmel.com and port it to your hardware.

Also, which module do you use? If it is something unamplified, then you may be seeing its true performance.

[muthukural001]

Hi Alex,

Is the time sync code support to use CCA feature in AT86RF212B to select channel automatically?



Regards,
Muthu

[ataradov]

I don't understand the question.

CCA is never used to select a channel. CCA is used to sense if selected channel is busy before transmitting. And it needs to be disabled for time-synchronized networks, since all devices know ahead of time that channel will be free, since they are transmitting in their personal time slot.

[muthukural001]

Hi Alex,
Thanks. I just want to know that the following is possible with the time synchronized network code.

Right now, I have assigned Channel number 5-914Mhz in the North American band for End nodes and Gateway by writing the corresponding register. So, It will form network at Channel 5.Instead of doing the above, Is there any automatic channel selection method which measures channels energy before forming network so that form the network on the channel that have less energy ?.


Thanks,
Muthu

[ataradov]

Just do a ED scan on all channels before you pick one.

But that's not super robust, since interference may be intermittent. You probably also want to make a decision to switch even when network is running, but nodes can detect loss of data.

Read the ZigBee spec, it has all of that described, so you can get some ideas from there.

[muthukural001]

Hi Alex,
Thanks.I will read the Zigbee spec.I have the following Question.


1.Assume,there are 10 nodes plus Gateway.Each will do ED scan on startup and select channel which is best.The channel to be selected by the nodes and Gateway should be same right in order to time sync network work ? . Please let me know that how channel selection of each nodes will go.



Regards,
Muthu