LX9-Spartan-Board

[Write_to_Smokegenerator]

Hello

I purchased the AVnet Spartan-6 LX9 Microboard it's not the newest board but not that expensive.
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm

I'm a beginner with FPGA's but i did learn some VHDL years ago, so i thought could be fun to do something.

After i learned that you don't have a licence for the softcore (i found that out while trying a tutorial) i was a little bit annoyed but can't be helped.
The getting started guide is quite nice also the test feature via ethernet was cool.
(If I wouldn't have a question this topic would be in product review^^)

So after I finally figured out how to program my VHDL code to that thing i decided to play a little bit with it, so i wanted to test the dip switch but then i saw the note that i should use the internal pulldown resistors if the resistor array isn't on the board (unfortunately mine is missing)

So my question is how can I use the internal Pulldown? I Searched for like an hour but I can't find any useful information about that part.

thanks in advance

cheers.

[nctnico]

You should be able to use the Xilinx SDK in order to get the softcore. The LX9 board serves as a dongle (hardware license key).

Anyway, the pin definitions are usually not setup from VHDL but from a UCF file. The UCF file holds the pin allocations and timing constraints.

[krenzo]

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf

This is the manual of Spartan 6's built-in components.  When you create a new VHDL file in ISE Project Navigator, you'll get the following at the top of your .vhd file:

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

You want to uncomment the last two lines (comments start with two hyphens) to be able to use Xilinx's built in components, and you only need this once at the top of your VHD file.  Now you can use Xilinx components like the pull-down resistor.  Look in that PDF file under Chapter 4 for "PULLDOWN", and it will give you VHDL code for how to use it in your design:

-- PULLDOWN: I/O Buffer Weak Pull-down
-- Spartan-6
-- Xilinx HDL Libraries Guide, version 12.4
PULLDOWN_inst : PULLDOWN
port map (
O => O -- Pulldown output (connect directly to top-level port)
);
-- End of PULLDOWN_inst instantiation

So you would insert that code into your design and change where it says "O => O" to "O => your_dip_switch_input_port" where "your_dip_switch_input_port" is the name you assigned to your dip switch's input port.

In Project Navigator, you can get a list of all components without having to refer back to the PDF.  If you look on the toolbar all the way to the right, there's a light bulb icon.  Click it, and then expand the VHDL list.  You'll get a list of all components and various helpful elements that are applicable to VHDL.  If you look at the picture I attached, you'll see where you can find the PULLDOWN component, and it will give you the necessary code for it in the right pane.

[andyg]

After i learned that you don't have a licence for the softcore (i found that out while trying a tutorial) i was a little bit annoyed but can't be helped.

Correct me if I'm wrong, but I thought the Microblaze soft core was free to use on any Xilinx part? (i.e doesn't require payment, but requires you to agree to those terms)

Never used it myself, but I have used Picoblaze which works under a similar license.

[joelby]

Correct me if I'm wrong, but I thought the Microblaze soft core was free to use on any Xilinx part? (i.e doesn't require payment, but requires you to agree to those terms)

Never used it myself, but I have used Picoblaze which works under a similar license.

Sometimes. The EDK (tool for configuring MicroBlaze and peripherals) and SDK (a version of Eclipse with compiler and graphical debugger) require a license. The LX9 Microboard comes with a device-locked SDK license. There are free GCC versions that will target MicroBlaze if you don't have an SDK license. I think it's EDK that comes with a MicroBlaze license that lets you configure, customise and use MicroBlaze cores.

Prior to ISE 13.4, there was something called the Simple MicroBlaze Microcontroller (SMM), which gave you a couple of pre-synthesised MicroBlaze cores with a few standard peripherals that you could use freely (as far as I could tell.. the license was never really clear about that). In 13.4, this was replaced with the MicroBlaze Micro Controller System (MCS), which is the same idea as SMM but it is included with WebPACK and the license terms were clarified somewhat.

[Write_to_Smokegenerator]

@ krenzo thanks so much, that's exactly what I was searching for.


@ andyg ,joelby was a little faster than me writing back (thank you joelby for reply). I don't know the details as much as him but


Anyways i post what i found regarding that:

 I met a guy from AVnet 3 weeks ago and he told me that the license costs about 500$

If you visit the AVnet Forum about the lx9 you can see 3-4 posts about the problem with licence issues.
http://community.em.avnet.com/t5/Spartan-6-LX9-MicroBoard/License-error-while-trying-Tutorial-1/td-p/2382

"The EDKxx tutorials require an XPS license, which is not included in the kit.  The XPS license is included in the full EDK suite (which includes XPS, SDK, and the MicroBlaze license)"

[joelby]

That sounds about right. The EDK was about $500 retail on Avnet last time I checked, which is probably out of the hobbyist's reach, but is pretty reasonable when you consider the cost of your time and how bad some of the open source alternatives are. Also I think the EDK comes with license for the Xilinx 10/100 Ethernet core, which is a classy bonus.

Hopefully the LX9 board comes with a pre-built MicroBlaze image that is correctly configured to use the board's RAM. If you have modest performance and memory requirements, MCS should be fine to get started with. If you want to start customising the processor and creating HDL peripherals, you'll need the EDK.

[Scrts]

Check project MilkyMist. They run LatticeMico 32bit softcore on Xilinx Spartan-6. Anyway, I am more happy with Nios.

[ocayaro]

I solved the problem differently. This method should work for almost any board, not just AVNET.

First, download the AVNET board-definition files from http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm You might need to register on the site and then search for XBD (i.e. Xilinx Board Definition) files for your board. I have included a ZIP file for AVNET's Spartan-6 LX9. Extract the files to the board directory (e.g. C:\Xilinx\13.4\ISE_DS\EDK\board\Avnet\), so that you have two subdirectories \boards and \ipxact containing the unzipped files.

Then, start up Xilinx's Project Navigator, create a project, select YOUR AVNET board that should now show. Then go to Project...New Source...Embedded Processor. Type in the name of the embedded processor, e.g. mb_system. Soon after Xilinx Platform Studio opens up (and likely complains about license. Ignore it. Answer "yes" to "....Do you want to create a base system using the BSB wizard?"

Then select "PLB..." radio button, and then you'll be guided though "Welcome", "Board" is AVNET Spartan-6 LX9 is preselected (or the one you chose earlier). Press "Next", "Next" until you get to "Peripherals".

Highlight all the peripherals on the left-side and click "Add". This will guarantee that all peripherals on the AVNET board will have definitions in the board UCF you are creating. Then click "Next". XPS creates the board definition files alongside all its other outputs, displays a summary of the system resources you are using. Click "Finish" and close XPS.

Go back to Project Navigator, then "Project...Add Source ..." and navigate to the folder with the name above e.g. "C:\Xilinx\Embedded\tutorial_02\mb_system\data" in my case. You will find "mb_system.ucf". That is the file you need. Add it to the project and once it is loaded, double click on it to view its contents. It should look something like this:


#  Avnet Spartan-6 LX9 MicroBoard
Net fpga_0_USB_UART_RX_pin LOC=R7 | IOSTANDARD = LVCMOS33;
Net fpga_0_USB_UART_TX_pin LOC=T7 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<0> LOC=P4 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<1> LOC=L6 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<2> LOC=F5 | IOSTANDARD = LVCMOS18;
Net fpga_0_LEDs_4Bits_GPIO_IO_O_pin<3> LOC=C2 | IOSTANDARD = LVCMOS18;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<0> LOC=B3 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<1> LOC=A3 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<2> LOC=B4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_DIP_Switch_4Bits_GPIO_IO_I_pin<3> LOC=A4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
Net fpga_0_SPI_FLASH_SCK_pin LOC=R15 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_MISO_pin LOC=R13 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_MOSI_pin LOC=T13 | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SS_pin LOC=V3  | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SPI_HOLDn_pin LOC=V14  | IOSTANDARD = LVCMOS33;
Net fpga_0_SPI_FLASH_SPI_Wn_pin LOC=T14  | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC =   H17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC =   L15 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC =   N17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC =   P17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC =   T17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC =   N16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC =   N15 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC =   P18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC =   M18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC =   N18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC =   T18 | IOSTANDARD = LVCMOS33 | TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC =   L17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC =   K18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC =   K17 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC =   J18 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC =   J16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC =   M16 | IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC =   L18 | IOSTANDARD = LVCMOS33;
Net fpga_0_CDCE913_I2C_Sda_pin LOC=U13  | IOSTANDARD = LVCMOS33 | PULLUP;
Net fpga_0_CDCE913_I2C_Scl_pin LOC=P12  | IOSTANDARD = LVCMOS33 | PULLUP;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 66666.7 kHz;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin  |  LOC=K15 | IOSTANDARD = LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=V4 | IOSTANDARD = LVCMOS33 | PULLDOWN;

###### microblaze_0
### Set Vccaux for S6LX9 MicroBoard to 3.3V ###
CONFIG VCCAUX = "3.3" ;


###### Ethernet_MAC
### Pull-ups on RXD are necessary to set the PHY AD to 11110b.  ###
###   Must keep the PHY from defaulting to PHY AD = 00000b      ###
###   because this is Isolate Mode                              ###
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> PULLUP;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> PULLUP;

---------------------------

Scream YEY! if this helped.

[ocayaro]

From within XPS you can of course leave out the peripherals that you are not using in your own project. Simply select them on the right hand side in the "Peripherals" window and click "Remove".

---------
Scream YEY! if this helped.