M68EC0x0IDP bus timing, looking for lost documentation

[legacy]

hi guys
I got a vintage development board, it comes with a pretty 68000 CPU, ram, serials, timers, everything is fine, the IDP-board was designed to provide a flexible, expandible platform for CPU evalutation, software development, and hardware development support. The basic functionality of the IDP can be supplement with a variety of standard IDP-bus products as well as customer defineded modules, so ... this board has a custom bus, handled by an fpga, I have no detailed documentation about, while I know, from the included paper, that up to 5 expansion modules are allowed, and MC688916 (PLL) clock synchronizer must be present on each I/O module to synchronize clocks to the bus clock (with 3nsec of clock skew).

The Slot Decoding goes easy because each I/O slot has its own slot enable signal generated by the FPGA on IDP motherboard. Each /SLOT is based on A27..A24, which reduces the address decoding overhead for the I/O module. The slot size is 16MB, so the slots are located at $0(n)0xx xxxx. Good!

I have already written a minimal BSP to take the control, everything is fine, but this board has no flash and no lan, so I'd like to develop an hardware module in order to attach 8Mbyte of NVRAM, plus a CS8900 ethernet.

In order to achieve this purpose, I need to develop a fsm with a little 5V tolerant CPLD (it handles the bus-slot), but about the IDP Bus Timing I have absolutely no documentation. What I have is a little blue card in where I can read the following:

Bus Timing

For information on M68EC0x0IDP bus timing, write the following address:

Motorola
High-Performance MPU Division
ATTN: IDP Technical Support
Mail Stop OE-33
6501 William Cannon Drive West
Austin, Texas 78735-8598 USA

I have already tried to contact the DNA division and they have told me that board is too obsolete for them, so they have no documentation.

does anyone know ? did anyone played with these boards ?


edit:
IDP boards were used and supported between 1992 (EC000) and 1997(EC060)

[marcopolo]

Hello,

I have a 000 and a 060 IDP boards but I only have the User's Manual v3.0 like you I think.

Marc

[legacy]

yep, I have those manuals v3 and they miss any other informations about the bus timing 

what are you doing with these boards, software project ? hardware project ?

I am planning to port Xinu, but I am also planning funny hw sub projects

I have already replaced the ROM1 (user-rom) with an Eprom Emulator, in order to upload at ~ 1Mbit/sec, becasue the mon's UART is too slow (19200bps), but I am also planning to plug in an ethernet module, and a FeRAM storage, within the 16Mbyte slot provided by the IDP bus. Ummm, also I'd like to add more ram and a GDB-stub.

Where have you found the 060 ? I got my 000 from an exchange-fair 

[marcopolo]

Hi,

I found the 2 boards on Ebay 2 years ago.
Projects planned:
- Trying GDB Remote debugging with target=IDP
- If it works, writing a small 68k monitor with the syntax of the IDP monitor for custom boards
- Develop a network board with AM79C90 for the IDP
- and later, develop VME custom boards. For the first, I think with MC68010 (or MC68012 from Ebay), MC68450 + MC68451

Marc

[legacy]

I think CS8900 is better lan chip, but … first we need the "bus timing" doc.
I am working on a GDB-stub, too, recycling a few lines from GNU.
I can send it to you, in case of need.

[legacy]

also, I'd like to hear about the Microtech Xray debugger, I have absolutely no information about it.
Someone experienced that want to have a little talk  ?

[marcopolo]

Yes, CS8900 is a better lan controller but it is not old enough for me 

Yes, I'm interested by a 68K gdb-stub, but I'm not in a hurry because for now I don't have spare time

From M68KIDP Product information:
XRAY+ and pROBE+ are highly integrated
with the real-time operating system to allow the user to debug on an operating-system level as well as on a
source level. Together, these development tools offer a complete real-time operating system solution for
the user. XRAY+, pROBE+, and pSOS+ are offered as options with the IDP. The pSOS+ and pROBE+ are
available through Motorola.

68K Tools with pSOS:
http://www.jive.nl/techinfo/su_master/TRM_Diag/PAH_files/full_JIVE%20on%20PAH%20%28Pah%29_16_june_2004/

[legacy]

Yes, CS8900 is a better lan controller but it is not old enough for me

The IDP bus has an interesting complexity.
It needs a fsm, so it needs a CPLD/FPGA
it needs a PLL
it has a lot of signals to be handled, 32bit address, 32bit data, spare other lines, no less than ~75 signals to be routed
it needs a connector of 3x32=96pins
it needs to be designed with signals @ 25Mhz
etc

so the PCB goes complex (especially if you want to support the burst mode)

I am afraid EagleCAD is not powerful enough to realize it, and I am afraid 2 layers are not enough.
I asked a senior, he answered that Altium is suggested, with no less than 4 layers.

So, in order to realize a PCB, I'd better reduce features into different boards (one board will be ethernet only, one board will be NVRAM only, etc) and on each board everything is simplified in order to reduce the complexity.

For example, the CS8900 chip is 8bit data line, Olimex has kits, embedded modules with the RJ45 + filter + transfer. It's just ready out of the box, you just need to wire it, while the AM79C90 chip is 16bit data line, and I can't find kits, so I will require more work in order to achieve a working ethernet module.

hobby-constraints are needed in order to achieve the purpose in terms of hobby resources (equipment, CAD licenses, budget, and time)

Yes, I'm interested by a 68K gdb-stub, but I'm not in a hurry because for now I don't have spare time

me too, but I am scheduling time slots.
I have two sub projects scheduled, the gdb-stub, and a new debug TAP I am developing for a SoftCore.

assigned priorities:
high - to my debug protocol and TAP (which is composed by C source for both linux and metalbare (e.g. 68k), and VHDL for fpga)
low - to gdb-stub (it's only C/metalbare)

XRAY+ and pROBE+ are highly integrated
…
available through Motorola.

I don't think we will find all of these equipments and tools, perhaps we will find something, but I am afraid it will take a lot of time, also a lot of time to understand, what is missing, what is not.

[legacy]

are you experienced with XRAY+ and pROBE+ ?

[marcopolo]

No 

[legacy]

oh well, I am really planning to plug a Logic Analyzer (LA) on the IDP bus in order to get-through-reversing its missing bus-timing, but, it's a bit "boring" to be hobby

It seems an IDP_ethernet_module was existing in an old Motorola inventory, but nobody (including Newart, obsolete parts reseller) has never had it for sale
This means no chance on ebay, and no real-hw IDP_module to be get through reverse engineering, we just have the IDP_controller on the motherboard (which phisically it's a QuickLogic FPGA, which oh my pants, wtf is QuickLogic?)

An other good thing I'd like to develop is an hyperdatalink dual port memory, something like 16Mbyte in where everything can be read/write (as byte,word,long) both from the IDP and from the remote host, at the maximal speed: 2-5-10Mbyte/sec for the IDP (burst mode is 10Mbyte/sec, but … you have to take care of the impedance, and a lot of things to go so fast without corrupting bits), and up to 5Mbit/sec (with an efficiency of 64Kbyte/(64Kbte+8) for the host. USB_UART_BULK driven.

It's extremely useful for debugging, it's damn faster than passing through GDB (which needs to use the CPU to read/write things from/into memory), while my Eprom Emulator is just useful to upload the ROM, up to 512Kbyte @ 100Kbyte/sec, 512Kbyte, the whole ROM,  in ~5 sec 

But this design implies a big FPGA (Spartan6?) + DDR RAM + CyChip + level shifters, a lot of level shifters, and a mixage of 3.3V logic + 5V logic, with a lot of SMD chips to be soldered: well, it's not the ideal design to be called "hobby" 

btw, the first attempt with the IDP hw

• making the PLL able to work with a BCLK of 12.5Mhz, with an expected local clock of 25Mhz, within 3nsec of clock skew (I am expecting a lot of noises and troubles during the prototyping activity)
• trying to inhibit the cache (which of course makes more sense with 060_IDP, which I do not have)
• understanding the minimal bus_timing to make the IDP_controll not to trap an hw_bus_error
• and in case ... writing a few assembly lines to handle the bus_error exception
• trying to play with DTACK to have delayed cycles (I need them for the hyperdatalink arbitration, hw semaphores)
• trying to play with the IDP controller untill I will achieve the correct data I/O
• and then ... when all of these will work, and I will have the idea of bus_timing, I will also try to achieve the burst mode
• I am also planning to give KiCAD a try, instead of using just EagleCAD

~ ~ ~

sent you an email, so you get my contact 

[legacy]

have you seen this ?

[marcopolo]

Yes and still expensive for old tools without support.

[marcopolo]

Maybe a VME board is a better choice than an IDP?
It's easy to find a MVME177 (68060) in the $50-$100 range and the bus is well documented.

[legacy]

Yes and still expensive for old tools without support.

damn true, I wonder WHY on the WHY they are asking 1K bucks for just an obsolete toolchain with a few printed books, if I were them I would be switched to ARM/PIC32/AVR8/AVR32, releasing everything is related to hc11/51/m68k for a cheap price, minded with the target of hobbyists and students. There is NO reason to sell obsolete toolchain (where obsolete means no support) for so high prices.

[legacy]

Maybe a VME board is a better choice than an IDP?

Usually a VME board requires a VME backplane, and usually it's double slot, 2xDIN96, and it eats more electricity, and it's bigger in size, but no doubts it's better than IDP about the cost, you can find many on ebay (while IDP is quite rare), and it's fully documented.

It's easy to find a MVME177 (68060) in the $50-$100 range and the bus is well documented.

I got an eye on a VME-060 board on ebay, it was an ELTEC board, more complex than IDP because it implemented hw semaphores, mail-boxes, and other stuff, also it was SMP with 2x060, and I have seen it was running VxWorks. I got a pdf from the seller, with the full manual, but I didn't purchase: too complex for me. He was asking 50 euro + shipping.

[legacy]

has someone experienced with Intermetrics' XDBTM source-level debugger ?

[legacy]

buuuuuump

anyone ?