Author Topic: MachXO2 gearing logic for LPDDR  (Read 2045 times)

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Offline kalhanaTopic starter

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MachXO2 gearing logic for LPDDR
« on: August 01, 2015, 11:37:39 pm »
Hi,

I'm trying to use a MachXO2 to interface to an LPDDR memory and want to use the onboard gearing logic for the DDR interface.
I read the TN1203 app note, but I can't find a way to just use the gearing logic only without the full Lattice's DDR controller from IPexpress.
Because I want to use my own custom DDR controller, with their HW I/O gearing interface.
Has anyone used it? Is it possible?

Thanks!
 

Offline kalhanaTopic starter

  • Contributor
  • Posts: 19
Re: MachXO2 gearing logic for LPDDR
« Reply #1 on: August 02, 2015, 01:53:39 am »
Ok, managed to figure it out and get Tx gearing to work.
It's under "DDR Generic"
More info was in TN1203, didn't read it properly!  :palm:
« Last Edit: August 02, 2015, 01:59:22 am by kalhana »
 


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