I would like to add a couple of points to try to clarify some confusion:
-a) First, the camera is in free-running clock. Meaning that the clock never stops. Therefore, the LP transitions don't happen and doesn't matter.
-b) I mentioned analog a few times and it's indeed a little bit confusing:
* FSA642 is an analog switch. Read the datasheet if you need to be convinced.
* An analog switch is probably impossible with a FPGA because FPGA have only digital IOs (read this:
http://www.edaboard.com/thread270986.html)
* But I still want to avoid deserialization/re-serialization of data. Therefore, I think that I need a clock as fast as the MIPI clock so that the 0s and 1s of both the input MIPI clock and data can be "assigned" to the output MIPI clock and data. Having the FPGA clock derived from the MIPI clock is definitely something I consider though it means that the MIPI input clock should be fed into some high-speed differential input CLOCK pins of bank 2.
So even if I manage to derive a clock from the MIPI clock, I'm still confused on what kind of input output (LVDS25E, LVDS25, MIPI) I should use, what will be the maximum speed (150MHz, 400Mhz, 450MHz) and if "assign output = input" will be enough.