Author Topic: Microchip EERAM  (Read 4260 times)

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Online Benta

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Re: Microchip EERAM
« Reply #25 on: December 08, 2016, 07:54:56 am »
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Keeping CE\ low while accessing multiple addresses is fairly common.
Most devices toggle RD\ (OE\) each cycle, but some of them do not, especially when doing burst reads:

Yes. But you are talking high-speed synchronous RAMs here.
This is about old-fashioned parallel asynchronuos SRAMs.

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Back in the day, I built a device from a kit which allowed the range of colours displayed by a BBC Micro to be expanded.

The 'beeb' had a digital TTL video output, ie. one bit each for red, green and blue, giving a palette of 8 colours.

To allow different colours to be shown on a compatible monitor, the device used the digital RGB signal to drive the address bits of a small capacity SRAM chip. The data outputs from the SRAM fed DACs for each channel, giving an analogue RGB signal that could show a much wider range of colours.

I no longer have a schematic, but I can easily imagine that the SRAM's CE was permanently enabled, and the data outputs simply changed in time with the video signal.

That's exactly what I meant when I referred to a "PROM-lookup type of circuit". And in your "beeb" extension it was probably a PROM, not an SRAM.

All that aside, the normal application for an asynchronous-interface parallel FRAM would not differ from an SRAM. That was my point.

Cheers.
 

Offline bktemp

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Re: Microchip EERAM
« Reply #26 on: December 08, 2016, 08:12:25 am »
Quote
Keeping CE\ low while accessing multiple addresses is fairly common.
Most devices toggle RD\ (OE\) each cycle, but some of them do not, especially when doing burst reads:

Yes. But you are talking high-speed synchronous RAMs here.
This is about old-fashioned parallel asynchronuos SRAMs.
No, I am talking about high-speed asynchronous SRAMs.
One example of a microcontroller using this type of bus cycle I know offhand is PIC24FJ256DA210 when external SRAM is being used for its build in display controller.
http://ww1.microchip.com/downloads/en/DeviceDoc/39730B.pdf
page 46
It keeps RD active (shown as active high in the example waveform) while reading a burst of 3 bytes, transferring 1 byte per clock cycle.
It also supports the conventional bus cycle with RD\ being pulsed once per access, but it is much slower.
 

Online Benta

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Re: Microchip EERAM
« Reply #27 on: December 08, 2016, 08:42:50 am »
Yes. Well. Right. That's of course a typical application for a 100 ns SRAM or FRAM.

'Nuff said.

 


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