Microcontroller with clocked 10-bit parallel input?

[MarkL]

Not sure if this is related, its just happened I'm in the middle of reading the new TI arm m4f mcu TM4C1294NCPDT datasheet since I just got the brand new TI Tiva C Series Launchpad EK-TM4C1294XL(Photo). There is a thread discussing this new TI product -> HERE.
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This is a nice chip (and a pretty big hammer for this problem).  I've evaluated Stellaris chips but never used one in a design.  I haven't been keeping up with them - thanks for pointing out the EPI.

I looked through the EPI section on the data sheet and I don't see where they provide an edge clock input (aka slave mode).  In what they call "Host-Bus Mode", they do provide a wait signal (RDYEN), but it's synchronized to the internal EPICLK and not to an incoming clock edge.

I know you said you're just picking this up too, but if there's some other mode you have in mind, please let me know.  (There's way too many MCUs out there!  Aaaah!)

[peter.mitchell]

http://www.parallaxsemiconductor.com/products/propellerchips

[MarkL]

http://www.parallaxsemiconductor.com/products/propellerchips

Ok, a little bit of a learning curve on this one since I don't know Spin.  And a solution doesn't pop out at me after perusing the Propeller data sheet and manual.

But I'm game to listen... How would you use the cogs to capture 10 input bits in parallel on an external clock edge?  If you've read the rest of this thread the timing constraints are pretty tight.

[Jeroen3]

There is SGPIO in some higher-end NXP parts.

[MarkL]

Ok - so the SGPIO on the LPC4300 series I think finally fits my application.  I can configure a 10-bit input port using 10 SGPIO slices.  And I get the FIFO as a bonus.

Thanks, Jeroen!

[David Hess]

If the data rate is not too high, then a pair of 74597 latched parallel to serial converters in the logic family of your choice can handle this sort of thing.  At higher data rates, 8-bit latches with tristate outputs would be faster.

[Jeroen3]

By default most 32 bit microcontrollers already have at least one 16 bit parallel input, some even 32 bit.
Just route all lines to a single IO port block (eg A_0 to A_15), then use interval or triggered DMA to read the input registers to a circular buffer.
Only when your datarate is reaching a burst speed of more then a factor of your MIPS rate you should be worried doing it "by software" like this.
But using dedicated hardware is probably much easier and faster, and more flexible since it won't be a easy choice to surrender a full IO port bank to gpio. There might be other features sharing a pin.

[lewis]

Does the display have all the data pins connected? These displays are very often used in 4-bit mode to save MCU I/O. You can then use a low end PIC with the 8-bit parallel slave port.

If it's used in 8-bit mode, use the parallel slave port on the 8 data bits, the LCD's 'E' becomes the clock, and you can use any two other port pins for the R/W and RS pins. Why? because the datasheet specifies a min hold time for these two pins of Tpw = 230ns after the low to high transition of 'E'. Plenty of time for 'E' to trigger an edge-enabled interrupt in the PIC and for the interrupt routine to poll these pins.

Come on dudes, all this talk of FPGAs and PSOCs is far too OTT for reading data being sent to an HD44780 display

[Jeroen3]

HD44780 can easily be captured and sent over RS232 by software using an 8 MHz ATMEGA32 chip, the wait states of those LCDs are massive.
However the goal seems to be an interface bridge. A hardware solution might be more fancy to focus more the following serial (wireless) interface